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Commit cecd902a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'next-samsung-devel-spi3' of... 

Merge branch 'next-samsung-devel-spi3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into samsung/cleanup
parents 7a09266c a153e31a

arch/arm/mach-s3c64xx/clock.c

+49 −31
Original line number Diff line number Diff line
@@ -183,18 +183,6 @@ static struct clk init_clocks_off[] = { 
		.parent		= &clk_p,

		.enable		= s3c64xx_pclk_ctrl,

		.ctrlbit	= S3C_CLKCON_PCLK_SPI1,

	}, {

		.name		= "spi_48m",

		.devname	= "s3c64xx-spi.0",

		.parent		= &clk_48m,

		.enable		= s3c64xx_sclk_ctrl,

		.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,

	}, {

		.name		= "spi_48m",

		.devname	= "s3c64xx-spi.1",

		.parent		= &clk_48m,

		.enable		= s3c64xx_sclk_ctrl,

		.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,

	}, {

		.name		= "48m",

		.devname	= "s3c-sdhci.0",
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = { 
	},

};



static struct clk clk_48m_spi0 = {

	.name		= "spi_48m",

	.devname	= "s3c64xx-spi.0",

	.parent		= &clk_48m,

	.enable		= s3c64xx_sclk_ctrl,

	.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,

};



static struct clk clk_48m_spi1 = {

	.name		= "spi_48m",

	.devname	= "s3c64xx-spi.1",

	.parent		= &clk_48m,

	.enable		= s3c64xx_sclk_ctrl,

	.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,

};



static struct clk init_clocks[] = {

	{

		.name		= "lcd",
@@ -590,25 +594,6 @@ static struct clksrc_clk clksrcs[] = { 
		.reg_src 	= { .reg = S3C_CLK_SRC, .shift = 5, .size = 2  },

		.reg_div	= { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4  },

		.sources	= &clkset_uhost,

	}, {

		.clk	= {

			.name		= "spi-bus",

			.devname	= "s3c64xx-spi.0",

			.ctrlbit        = S3C_CLKCON_SCLK_SPI0,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },

		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },

		.sources	= &clkset_spi_mmc,

	}, {

		.clk	= {

			.name		= "spi-bus",

			.devname	= "s3c64xx-spi.1",

			.enable		= s3c64xx_sclk_ctrl,

		},

		.reg_src	= { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },

		.reg_div	= { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },

		.sources	= &clkset_spi_mmc,

	}, {

		.clk	= {

			.name		= "audio-bus",
@@ -708,6 +693,30 @@ static struct clksrc_clk clk_sclk_mmc2 = { 
	.sources	= &clkset_spi_mmc,

};



static struct clksrc_clk clk_sclk_spi0 = {

	.clk	= {

		.name		= "spi-bus",

		.devname	= "s3c64xx-spi.0",

		.ctrlbit	= S3C_CLKCON_SCLK_SPI0,

		.enable		= s3c64xx_sclk_ctrl,

	},

	.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },

	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },

	.sources = &clkset_spi_mmc,

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk	= {

		.name		= "spi-bus",

		.devname	= "s3c64xx-spi.1",

		.ctrlbit	= S3C_CLKCON_SCLK_SPI1,

		.enable		= s3c64xx_sclk_ctrl,

	},

	.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },

	.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },

	.sources = &clkset_spi_mmc,

};



/* Clock initialisation code */



static struct clksrc_clk *init_parents[] = {
@@ -721,12 +730,16 @@ static struct clksrc_clk *clksrc_cdev[] = { 
	&clk_sclk_mmc0,

	&clk_sclk_mmc1,

	&clk_sclk_mmc2,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

};



static struct clk *clk_cdev[] = {

	&clk_hsmmc0,

	&clk_hsmmc1,

	&clk_hsmmc2,

	&clk_48m_spi0,

	&clk_48m_spi1,

};



static struct clk_lookup s3c64xx_clk_lookup[] = {
@@ -738,6 +751,11 @@ static struct clk_lookup s3c64xx_clk_lookup[] = { 
	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),

	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),

};



#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

arch/arm/mach-s3c64xx/dev-spi.c

+0 −7
Original line number Diff line number Diff line
@@ -24,12 +24,6 @@ 
#include <plat/gpio-cfg.h>

#include <plat/devs.h>



static char *spi_src_clks[] = {

	[S3C64XX_SPI_SRCCLK_PCLK] = "pclk",

	[S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",

	[S3C64XX_SPI_SRCCLK_48M] = "spi_48m",

};



/* SPI Controller platform_devices */



/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
@@ -176,5 +170,4 @@ void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) 


	pd->num_cs = num_cs;

	pd->src_clk_nr = src_clk_nr;

	pd->src_clk_name = spi_src_clks[src_clk_nr];

}

arch/arm/mach-s5p64x0/clock-s5p6440.c

+29 −32
Original line number Diff line number Diff line
@@ -267,18 +267,6 @@ static struct clk init_clocks_off[] = { 
		.parent		= &clk_pclk.clk,

		.enable		= s5p64x0_pclk_ctrl,

		.ctrlbit	= (1 << 31),

	}, {

		.name		= "sclk_spi_48",

		.devname	= "s3c64xx-spi.0",

		.parent		= &clk_48m,

		.enable		= s5p64x0_sclk_ctrl,

		.ctrlbit	= (1 << 22),

	}, {

		.name		= "sclk_spi_48",

		.devname	= "s3c64xx-spi.1",

		.parent		= &clk_48m,

		.enable		= s5p64x0_sclk_ctrl,

		.ctrlbit	= (1 << 23),

	}, {

		.name		= "mmc_48m",

		.devname	= "s3c-sdhci.0",
@@ -419,26 +407,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.0",

			.ctrlbit	= (1 << 20),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.1",

			.ctrlbit	= (1 << 21),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group1,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_post",
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = { 
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi0 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.0",

		.ctrlbit	= (1 << 20),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group1,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.1",

		.ctrlbit	= (1 << 21),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group1,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

};



/* Clock initialization code */

static struct clksrc_clk *sysclks[] = {

	&clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = { 


static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uclk,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

};



static struct clk_lookup s5p6440_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),

};



void __init_or_cpufreq s5p6440_setup_clocks(void)

arch/arm/mach-s5p64x0/clock-s5p6450.c

+29 −20
Original line number Diff line number Diff line
@@ -441,26 +441,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.0",

			.ctrlbit	= (1 << 20),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_spi",

			.devname	= "s3c64xx-spi.1",

			.ctrlbit	= (1 << 21),

			.enable		= s5p64x0_sclk_ctrl,

		},

		.sources = &clkset_group2,

		.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

		.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_fimc",
@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = { 
	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi0 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.0",

		.ctrlbit	= (1 << 20),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group2,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },

};



static struct clksrc_clk clk_sclk_spi1 = {

	.clk	= {

		.name		= "sclk_spi",

		.devname	= "s3c64xx-spi.1",

		.ctrlbit	= (1 << 21),

		.enable		= s5p64x0_sclk_ctrl,

	},

	.sources = &clkset_group2,

	.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },

	.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },

};



static struct clksrc_clk *clksrc_cdev[] = {

	&clk_sclk_uclk,

	&clk_sclk_spi0,

	&clk_sclk_spi1,

};



static struct clk_lookup s5p6450_clk_lookup[] = {

	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),

	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),

	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),

	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),

	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),

};



/* Clock initialization code */

arch/arm/mach-s5p64x0/dev-spi.c

+0 −6
Original line number Diff line number Diff line
@@ -25,11 +25,6 @@ 
#include <plat/s3c64xx-spi.h>

#include <plat/gpio-cfg.h>



static char *s5p64x0_spi_src_clks[] = {

	[S5P64X0_SPI_SRCCLK_PCLK] = "pclk",

	[S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",

};



/* SPI Controller platform_devices */



/* Since we emulate multi-cs capability, we do not touch the CS.
@@ -220,5 +215,4 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) 


	pd->num_cs = num_cs;

	pd->src_clk_nr = src_clk_nr;

	pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];

}