Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a09266c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'next-samsung-cleanup-mmc2' of... 

Merge branch 'next-samsung-cleanup-mmc2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into samsung/cleanup
parents 4eb82199 4346b6d9

arch/arm/mach-exynos/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -58,6 +58,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o 
obj-$(CONFIG_EXYNOS4_SETUP_I2C6)	+= setup-i2c6.o

obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o

obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o

obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)	+= setup-sdhci.o

obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o

obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)	+= setup-usb-phy.o

arch/arm/mach-exynos/clock.c

+52 −36
Original line number Diff line number Diff line
@@ -1154,42 +1154,6 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &clkset_mout_mfc,

		.reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },

		.reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.devname	= "s3c-sdhci.0",

			.parent		= &clk_dout_mmc0.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 0),

		},

		.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },

	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.devname	= "s3c-sdhci.1",

			.parent         = &clk_dout_mmc1.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 4),

		},

		.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },

	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.devname	= "s3c-sdhci.2",

			.parent         = &clk_dout_mmc2.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 8),

		},

		.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },

	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.devname	= "s3c-sdhci.3",

			.parent         = &clk_dout_mmc3.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 12),

		},

		.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },

	}, {

		.clk		= {

			.name		= "sclk_dwmmc",
@@ -1249,6 +1213,50 @@ static struct clksrc_clk clk_sclk_uart3 = { 
	.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },

};



static struct clksrc_clk clk_sclk_mmc0 = {

	.clk		= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.0",

		.parent		= &clk_dout_mmc0.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 0),

	},

	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },

};



static struct clksrc_clk clk_sclk_mmc1 = {

	.clk		= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.1",

		.parent         = &clk_dout_mmc1.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 4),

	},

	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },

};



static struct clksrc_clk clk_sclk_mmc2 = {

	.clk		= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.2",

		.parent         = &clk_dout_mmc2.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 8),

	},

	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },

};



static struct clksrc_clk clk_sclk_mmc3 = {

	.clk		= {

		.name		= "sclk_mmc",

		.devname	= "s3c-sdhci.3",

		.parent         = &clk_dout_mmc3.clk,

		.enable		= exynos4_clksrc_mask_fsys_ctrl,

		.ctrlbit	= (1 << 12),

	},

	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },

};



/* Clock initialization code */

static struct clksrc_clk *sysclks[] = {

	&clk_mout_apll,
@@ -1293,6 +1301,10 @@ static struct clksrc_clk *clksrc_cdev[] = { 
	&clk_sclk_uart1,

	&clk_sclk_uart2,

	&clk_sclk_uart3,

	&clk_sclk_mmc0,

	&clk_sclk_mmc1,

	&clk_sclk_mmc2,

	&clk_sclk_mmc3,

};



static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1300,6 +1312,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { 
	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),

	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),

	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),

	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),

	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),

	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),

};

arch/arm/mach-exynos/setup-sdhci.c

deleted100644 → 0
+0 −22
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-exynos4/setup-sdhci.c

 *

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include <linux/types.h>



/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */



char *exynos4_hsmmc_clksrcs[4] = {

	[0] = NULL,

	[1] = NULL,

	[2] = "sclk_mmc",	/* mmc_bus */

	[3] = NULL,

};

arch/arm/mach-s3c2416/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o 
#obj-$(CONFIG_S3C2416_DMA)	+= dma.o



# Device setup

obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o

obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o



# Machine support

arch/arm/mach-s3c2416/clock.c

+37 −31
Original line number Diff line number Diff line
@@ -90,8 +90,7 @@ static struct clksrc_clk hsmmc_div[] = { 
	},

};



static struct clksrc_clk hsmmc_mux[] = {

	[0] = {

static struct clksrc_clk hsmmc_mux0 = {

	.clk	= {

		.name		= "hsmmc-if",

		.devname	= "s3c-sdhci.0",
@@ -106,8 +105,9 @@ static struct clksrc_clk hsmmc_mux[] = { 
		},

	},

	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },

	},

	[1] = {

};



static struct clksrc_clk hsmmc_mux1 = {

	.clk	= {

		.name		= "hsmmc-if",

		.devname	= "s3c-sdhci.1",
@@ -122,7 +122,6 @@ static struct clksrc_clk hsmmc_mux[] = { 
		},

	},

	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },

	},

};



static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = { 
	&hsspi_mux,

	&hsmmc_div[0],

	&hsmmc_div[1],

	&hsmmc_mux[0],

	&hsmmc_mux[1],

	&hsmmc_mux0,

	&hsmmc_mux1,

};



static struct clk_lookup s3c2416_clk_lookup[] = {

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),

	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),

	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),

};



void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal) 
		s3c_register_clksrc(clksrcs[ptr], 1);



	s3c24xx_register_clock(&hsmmc0_clk);

	clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));



	s3c_pwmclk_init();