Loading arch/arm/boot/dts/qcom/msm8953.dtsi +5 −2 Original line number Diff line number Diff line Loading @@ -2109,6 +2109,7 @@ "ref_clk_addr", "tcsr_phy_clk_scheme_sel"; USB3_GDSC-supply = <&gdsc_usb30>; vdd-supply = <&pm8953_l3>; vdda18-supply = <&pm8953_l7>; vdda33-supply = <&pm8953_l13>; Loading @@ -2130,10 +2131,12 @@ clocks = <&clock_gcc clk_bb_clk1>, <&clock_gcc clk_gcc_qusb_ref_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_qusb2_phy_reset>; <&clock_gcc clk_gcc_qusb2_phy_reset>, <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, <&clock_gcc clk_gcc_usb30_master_clk>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset"; "phy_reset", "iface_clk", "core_clk"; }; Loading Loading
arch/arm/boot/dts/qcom/msm8953.dtsi +5 −2 Original line number Diff line number Diff line Loading @@ -2109,6 +2109,7 @@ "ref_clk_addr", "tcsr_phy_clk_scheme_sel"; USB3_GDSC-supply = <&gdsc_usb30>; vdd-supply = <&pm8953_l3>; vdda18-supply = <&pm8953_l7>; vdda33-supply = <&pm8953_l13>; Loading @@ -2130,10 +2131,12 @@ clocks = <&clock_gcc clk_bb_clk1>, <&clock_gcc clk_gcc_qusb_ref_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_qusb2_phy_reset>; <&clock_gcc clk_gcc_qusb2_phy_reset>, <&clock_gcc clk_gcc_pcnoc_usb3_axi_clk>, <&clock_gcc clk_gcc_usb30_master_clk>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset"; "phy_reset", "iface_clk", "core_clk"; }; Loading