Loading Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt +5 −0 Original line number Diff line number Diff line Loading @@ -186,6 +186,11 @@ IBB subnode optional properties: already. If it it not specified, then output voltage can be configured to any value in the allowed limit. - qcom,output-voltage-one-pulse The expected voltage (in mV) of VDISN signal on the first SWIRE pulse. This property can be specified only if 'qpnp,swire-control' is defined. The minimum and maximum values are 1400mV and 7700mV. Example: qcom,pmi8994@3 { Loading drivers/regulator/qpnp-labibb-regulator.c +44 −0 Original line number Diff line number Diff line Loading @@ -138,6 +138,7 @@ #define REG_IBB_PWRUP_PWRDN_CTL_1 0x58 #define REG_IBB_PWRUP_PWRDN_CTL_2 0x59 #define REG_IBB_SOFT_START_CTL 0x5F #define REG_IBB_SWIRE_CTL 0x5A #define REG_IBB_SPARE_CTL 0x60 #define REG_IBB_NLIMIT_DAC 0x61 Loading Loading @@ -195,6 +196,14 @@ #define IBB_BYPASS_PWRDN_DLY2_BIT BIT(5) #define IBB_FAST_STARTUP BIT(3) /* REG_IBB_SWIRE_CTL */ #define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS 6 #define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK \ ((1 << IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS) - 1) #define MAX_OUTPUT_PULSE_VOLTAGE_MV 7700 #define MIN_OUTPUT_PULSE_VOLTAGE_MV 1400 #define OUTPUT_VOLTAGE_STEP_MV 100 /* REG_IBB_NLIMIT_DAC */ #define IBB_NLIMIT_DAC_EN 0x0 #define IBB_NLIMIT_DAC_DISABLE 0x5 Loading Loading @@ -2158,6 +2167,41 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, labibb->ttw_en = false; } if (of_find_property(of_node, "qcom,output-voltage-one-pulse", NULL)) { if (!labibb->swire_control) { pr_err("Invalid property 'qcom,output-voltage-one-pulse', valid only in SWIRE config\n"); return -EINVAL; } rc = of_property_read_u32(of_node, "qcom,output-voltage-one-pulse", &tmp); if (rc) { pr_err("failed to read qcom,output-voltage-one-pulse rc=%d\n", rc); return rc; } if (tmp > MAX_OUTPUT_PULSE_VOLTAGE_MV || tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) { pr_err("Invalid one-pulse voltage range %d\n", tmp); return -EINVAL; } /* * Set the output voltage 100mV lower as the IBB HW module * counts one pulse less in SWIRE mode. */ val = DIV_ROUND_UP((tmp - MIN_OUTPUT_PULSE_VOLTAGE_MV), OUTPUT_VOLTAGE_STEP_MV) - 1; rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + REG_IBB_SWIRE_CTL, IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, val); if (rc) { pr_err("qpnp_labiibb_write register %x failed rc = %d\n", REG_IBB_SWIRE_CTL, rc); return rc; } } rc = qpnp_labibb_read(labibb, &ibb_enable_ctl, labibb->ibb_base + REG_IBB_ENABLE_CTL, 1); if (rc) { Loading Loading
Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt +5 −0 Original line number Diff line number Diff line Loading @@ -186,6 +186,11 @@ IBB subnode optional properties: already. If it it not specified, then output voltage can be configured to any value in the allowed limit. - qcom,output-voltage-one-pulse The expected voltage (in mV) of VDISN signal on the first SWIRE pulse. This property can be specified only if 'qpnp,swire-control' is defined. The minimum and maximum values are 1400mV and 7700mV. Example: qcom,pmi8994@3 { Loading
drivers/regulator/qpnp-labibb-regulator.c +44 −0 Original line number Diff line number Diff line Loading @@ -138,6 +138,7 @@ #define REG_IBB_PWRUP_PWRDN_CTL_1 0x58 #define REG_IBB_PWRUP_PWRDN_CTL_2 0x59 #define REG_IBB_SOFT_START_CTL 0x5F #define REG_IBB_SWIRE_CTL 0x5A #define REG_IBB_SPARE_CTL 0x60 #define REG_IBB_NLIMIT_DAC 0x61 Loading Loading @@ -195,6 +196,14 @@ #define IBB_BYPASS_PWRDN_DLY2_BIT BIT(5) #define IBB_FAST_STARTUP BIT(3) /* REG_IBB_SWIRE_CTL */ #define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS 6 #define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK \ ((1 << IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS) - 1) #define MAX_OUTPUT_PULSE_VOLTAGE_MV 7700 #define MIN_OUTPUT_PULSE_VOLTAGE_MV 1400 #define OUTPUT_VOLTAGE_STEP_MV 100 /* REG_IBB_NLIMIT_DAC */ #define IBB_NLIMIT_DAC_EN 0x0 #define IBB_NLIMIT_DAC_DISABLE 0x5 Loading Loading @@ -2158,6 +2167,41 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, labibb->ttw_en = false; } if (of_find_property(of_node, "qcom,output-voltage-one-pulse", NULL)) { if (!labibb->swire_control) { pr_err("Invalid property 'qcom,output-voltage-one-pulse', valid only in SWIRE config\n"); return -EINVAL; } rc = of_property_read_u32(of_node, "qcom,output-voltage-one-pulse", &tmp); if (rc) { pr_err("failed to read qcom,output-voltage-one-pulse rc=%d\n", rc); return rc; } if (tmp > MAX_OUTPUT_PULSE_VOLTAGE_MV || tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) { pr_err("Invalid one-pulse voltage range %d\n", tmp); return -EINVAL; } /* * Set the output voltage 100mV lower as the IBB HW module * counts one pulse less in SWIRE mode. */ val = DIV_ROUND_UP((tmp - MIN_OUTPUT_PULSE_VOLTAGE_MV), OUTPUT_VOLTAGE_STEP_MV) - 1; rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + REG_IBB_SWIRE_CTL, IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, val); if (rc) { pr_err("qpnp_labiibb_write register %x failed rc = %d\n", REG_IBB_SWIRE_CTL, rc); return rc; } } rc = qpnp_labibb_read(labibb, &ibb_enable_ctl, labibb->ibb_base + REG_IBB_ENABLE_CTL, 1); if (rc) { Loading