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Commit cc377fc7 authored by Runmin Wang's avatar Runmin Wang
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ARM: dts: msm: Add entries for dumping L1 cache for msmcobalt 



Add dts support to dump L1 cache in order to analyse data
corruption.

Change-Id: Ief343619c865f2d05ffc28f7955dffceb00f9a7f
Signed-off-by: default avatarRunmin Wang <runminw@codeaurora.org>
parent 184e2ced
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