Loading drivers/clk/msm/clock-mmss-8996.c +8 −0 Original line number Diff line number Diff line Loading @@ -428,6 +428,7 @@ static struct clk_freq_tbl ftbl_csi0_clk_src[] = { static struct clk_freq_tbl ftbl_csi0_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -437,6 +438,7 @@ static struct clk_freq_tbl ftbl_csi0_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -562,6 +564,7 @@ static struct clk_freq_tbl ftbl_csi1_clk_src[] = { static struct clk_freq_tbl ftbl_csi1_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -571,6 +574,7 @@ static struct clk_freq_tbl ftbl_csi1_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -604,6 +608,7 @@ static struct clk_freq_tbl ftbl_csi2_clk_src[] = { static struct clk_freq_tbl ftbl_csi2_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -613,6 +618,7 @@ static struct clk_freq_tbl ftbl_csi2_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -646,6 +652,7 @@ static struct clk_freq_tbl ftbl_csi3_clk_src[] = { static struct clk_freq_tbl ftbl_csi3_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -655,6 +662,7 @@ static struct clk_freq_tbl ftbl_csi3_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading
drivers/clk/msm/clock-mmss-8996.c +8 −0 Original line number Diff line number Diff line Loading @@ -428,6 +428,7 @@ static struct clk_freq_tbl ftbl_csi0_clk_src[] = { static struct clk_freq_tbl ftbl_csi0_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -437,6 +438,7 @@ static struct clk_freq_tbl ftbl_csi0_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -562,6 +564,7 @@ static struct clk_freq_tbl ftbl_csi1_clk_src[] = { static struct clk_freq_tbl ftbl_csi1_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -571,6 +574,7 @@ static struct clk_freq_tbl ftbl_csi1_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -604,6 +608,7 @@ static struct clk_freq_tbl ftbl_csi2_clk_src[] = { static struct clk_freq_tbl ftbl_csi2_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -613,6 +618,7 @@ static struct clk_freq_tbl ftbl_csi2_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading Loading @@ -646,6 +652,7 @@ static struct clk_freq_tbl ftbl_csi3_clk_src[] = { static struct clk_freq_tbl ftbl_csi3_clk_src_v2[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading @@ -655,6 +662,7 @@ static struct clk_freq_tbl ftbl_csi3_clk_src_v3[] = { F_MM( 100000000, mmsscc_gpll0_div, 3, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 266666667, mmpll0_out_main, 3, 0, 0), F_MM( 320000000, mmpll4_out_main, 3, 0, 0), F_MM( 480000000, mmpll4_out_main, 2, 0, 0), F_MM( 600000000, mmsscc_gpll0, 1, 0, 0), F_END Loading