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Commit cb00f7c1 authored by Francisco Jerez's avatar Francisco Jerez Committed by Ben Skeggs
Browse files

drm/nouveau: Pre-G80 tiling support. 



Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
parent 588d7d12

drivers/gpu/drm/nouveau/nouveau_drv.h

+18 −0
Original line number Diff line number Diff line
@@ -277,8 +277,13 @@ struct nouveau_timer_engine { 
};



struct nouveau_fb_engine {

	int num_tiles;



	int  (*init)(struct drm_device *dev);

	void (*takedown)(struct drm_device *dev);



	void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,

				 uint32_t size, uint32_t pitch);

};



struct nouveau_fifo_engine {
@@ -332,6 +337,9 @@ struct nouveau_pgraph_engine { 
	void (*destroy_context)(struct nouveau_channel *);

	int  (*load_context)(struct nouveau_channel *);

	int  (*unload_context)(struct drm_device *);



	void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,

				  uint32_t size, uint32_t pitch);

};



struct nouveau_engine {
@@ -881,10 +889,14 @@ extern void nv04_fb_takedown(struct drm_device *); 
/* nv10_fb.c */

extern int  nv10_fb_init(struct drm_device *);

extern void nv10_fb_takedown(struct drm_device *);

extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,

				      uint32_t, uint32_t);



/* nv40_fb.c */

extern int  nv40_fb_init(struct drm_device *);

extern void nv40_fb_takedown(struct drm_device *);

extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,

				      uint32_t, uint32_t);



/* nv04_fifo.c */

extern int  nv04_fifo_init(struct drm_device *);
@@ -945,6 +957,8 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *); 
extern int  nv10_graph_load_context(struct nouveau_channel *);

extern int  nv10_graph_unload_context(struct drm_device *);

extern void nv10_graph_context_switch(struct drm_device *);

extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,

					 uint32_t, uint32_t);



/* nv20_graph.c */

extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
@@ -956,6 +970,8 @@ extern int nv20_graph_unload_context(struct drm_device *); 
extern int  nv20_graph_init(struct drm_device *);

extern void nv20_graph_takedown(struct drm_device *);

extern int  nv30_graph_init(struct drm_device *);

extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,

					 uint32_t, uint32_t);



/* nv40_graph.c */

extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
@@ -967,6 +983,8 @@ extern void nv40_graph_destroy_context(struct nouveau_channel *); 
extern int  nv40_graph_load_context(struct nouveau_channel *);

extern int  nv40_graph_unload_context(struct drm_device *);

extern void nv40_grctx_init(struct nouveau_grctx *);

extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,

					 uint32_t, uint32_t);



/* nv50_graph.c */

extern struct nouveau_pgraph_object_class nv50_graph_grclass[];

drivers/gpu/drm/nouveau/nouveau_reg.h

+8 −8
Original line number Diff line number Diff line
@@ -349,19 +349,19 @@ 
#define NV04_PGRAPH_BLEND                                  0x00400824

#define NV04_PGRAPH_STORED_FMT                             0x00400830

#define NV04_PGRAPH_PATT_COLORRAM                          0x00400900

#define NV40_PGRAPH_TILE0(i)                               (0x00400900 + (i*16))

#define NV40_PGRAPH_TLIMIT0(i)                             (0x00400904 + (i*16))

#define NV40_PGRAPH_TSIZE0(i)                              (0x00400908 + (i*16))

#define NV40_PGRAPH_TSTATUS0(i)                            (0x0040090C + (i*16))

#define NV20_PGRAPH_TILE(i)                                (0x00400900 + (i*16))

#define NV20_PGRAPH_TLIMIT(i)                              (0x00400904 + (i*16))

#define NV20_PGRAPH_TSIZE(i)                               (0x00400908 + (i*16))

#define NV20_PGRAPH_TSTATUS(i)                             (0x0040090C + (i*16))

#define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))

#define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))

#define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))

#define NV10_PGRAPH_TSTATUS(i)                             (0x00400B0C + (i*16))

#define NV04_PGRAPH_U_RAM                                  0x00400D00

#define NV47_PGRAPH_TILE0(i)                               (0x00400D00 + (i*16))

#define NV47_PGRAPH_TLIMIT0(i)                             (0x00400D04 + (i*16))

#define NV47_PGRAPH_TSIZE0(i)                              (0x00400D08 + (i*16))

#define NV47_PGRAPH_TSTATUS0(i)                            (0x00400D0C + (i*16))

#define NV47_PGRAPH_TILE(i)                                (0x00400D00 + (i*16))

#define NV47_PGRAPH_TLIMIT(i)                              (0x00400D04 + (i*16))

#define NV47_PGRAPH_TSIZE(i)                               (0x00400D08 + (i*16))

#define NV47_PGRAPH_TSTATUS(i)                             (0x00400D0C + (i*16))

#define NV04_PGRAPH_V_RAM                                  0x00400D40

#define NV04_PGRAPH_W_RAM                                  0x00400D80

#define NV10_PGRAPH_COMBINER0_IN_ALPHA                     0x00400E40

drivers/gpu/drm/nouveau/nouveau_state.c

+8 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->timer.takedown		= nv04_timer_takedown;

		engine->fb.init			= nv10_fb_init;

		engine->fb.takedown		= nv10_fb_takedown;

		engine->fb.set_region_tiling	= nv10_fb_set_region_tiling;

		engine->graph.grclass		= nv10_graph_grclass;

		engine->graph.init		= nv10_graph_init;

		engine->graph.takedown		= nv10_graph_takedown;
@@ -111,6 +112,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->graph.fifo_access	= nv04_graph_fifo_access;

		engine->graph.load_context	= nv10_graph_load_context;

		engine->graph.unload_context	= nv10_graph_unload_context;

		engine->graph.set_region_tiling	= nv10_graph_set_region_tiling;

		engine->fifo.channels		= 32;

		engine->fifo.init		= nv10_fifo_init;

		engine->fifo.takedown		= nouveau_stub_takedown;
@@ -143,6 +145,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->timer.takedown		= nv04_timer_takedown;

		engine->fb.init			= nv10_fb_init;

		engine->fb.takedown		= nv10_fb_takedown;

		engine->fb.set_region_tiling	= nv10_fb_set_region_tiling;

		engine->graph.grclass		= nv20_graph_grclass;

		engine->graph.init		= nv20_graph_init;

		engine->graph.takedown		= nv20_graph_takedown;
@@ -152,6 +155,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->graph.fifo_access	= nv04_graph_fifo_access;

		engine->graph.load_context	= nv20_graph_load_context;

		engine->graph.unload_context	= nv20_graph_unload_context;

		engine->graph.set_region_tiling	= nv20_graph_set_region_tiling;

		engine->fifo.channels		= 32;

		engine->fifo.init		= nv10_fifo_init;

		engine->fifo.takedown		= nouveau_stub_takedown;
@@ -184,6 +188,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->timer.takedown		= nv04_timer_takedown;

		engine->fb.init			= nv10_fb_init;

		engine->fb.takedown		= nv10_fb_takedown;

		engine->fb.set_region_tiling	= nv10_fb_set_region_tiling;

		engine->graph.grclass		= nv30_graph_grclass;

		engine->graph.init		= nv30_graph_init;

		engine->graph.takedown		= nv20_graph_takedown;
@@ -193,6 +198,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->graph.destroy_context	= nv20_graph_destroy_context;

		engine->graph.load_context	= nv20_graph_load_context;

		engine->graph.unload_context	= nv20_graph_unload_context;

		engine->graph.set_region_tiling	= nv20_graph_set_region_tiling;

		engine->fifo.channels		= 32;

		engine->fifo.init		= nv10_fifo_init;

		engine->fifo.takedown		= nouveau_stub_takedown;
@@ -226,6 +232,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->timer.takedown		= nv04_timer_takedown;

		engine->fb.init			= nv40_fb_init;

		engine->fb.takedown		= nv40_fb_takedown;

		engine->fb.set_region_tiling	= nv40_fb_set_region_tiling;

		engine->graph.grclass		= nv40_graph_grclass;

		engine->graph.init		= nv40_graph_init;

		engine->graph.takedown		= nv40_graph_takedown;
@@ -235,6 +242,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->graph.destroy_context	= nv40_graph_destroy_context;

		engine->graph.load_context	= nv40_graph_load_context;

		engine->graph.unload_context	= nv40_graph_unload_context;

		engine->graph.set_region_tiling	= nv40_graph_set_region_tiling;

		engine->fifo.channels		= 32;

		engine->fifo.init		= nv40_fifo_init;

		engine->fifo.takedown		= nouveau_stub_takedown;

drivers/gpu/drm/nouveau/nv10_fb.c

+26 −6
Original line number Diff line number Diff line
@@ -3,17 +3,37 @@ 
#include "nouveau_drv.h"

#include "nouveau_drm.h"



void

nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,

			  uint32_t size, uint32_t pitch)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	uint32_t limit = max(1u, addr + size) - 1;



	if (pitch) {

		if (dev_priv->card_type >= NV_20)

			addr |= 1;

		else

			addr |= 1 << 31;

	}



	nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);

	nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);

	nv_wr32(dev, NV10_PFB_TILE(i), addr);

}



int

nv10_fb_init(struct drm_device *dev)

{

	uint32_t fb_bar_size;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;

	int i;



	fb_bar_size = drm_get_resource_len(dev, 0) - 1;

	for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {

		nv_wr32(dev, NV10_PFB_TILE(i), 0);

		nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);

	}

	pfb->num_tiles = NV10_PFB_TILE__SIZE;



	/* Turn all the tiling regions off. */

	for (i = 0; i < pfb->num_tiles; i++)

		pfb->set_region_tiling(dev, i, 0, 0, 0);



	return 0;

}

drivers/gpu/drm/nouveau/nv10_graph.c

+17 −11
Original line number Diff line number Diff line
@@ -807,6 +807,20 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan) 
	chan->pgraph_ctx = NULL;

}



void

nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,

			     uint32_t size, uint32_t pitch)

{

	uint32_t limit = max(1u, addr + size) - 1;



	if (pitch)

		addr |= 1 << 31;



	nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit);

	nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch);

	nv_wr32(dev, NV10_PGRAPH_TILE(i), addr);

}



int nv10_graph_init(struct drm_device *dev)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -838,17 +852,9 @@ int nv10_graph_init(struct drm_device *dev) 
	} else

		nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);



	/* copy tile info from PFB */

	for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {

		nv_wr32(dev, NV10_PGRAPH_TILE(i),

					nv_rd32(dev, NV10_PFB_TILE(i)));

		nv_wr32(dev, NV10_PGRAPH_TLIMIT(i),

					nv_rd32(dev, NV10_PFB_TLIMIT(i)));

		nv_wr32(dev, NV10_PGRAPH_TSIZE(i),

					nv_rd32(dev, NV10_PFB_TSIZE(i)));

		nv_wr32(dev, NV10_PGRAPH_TSTATUS(i),

					nv_rd32(dev, NV10_PFB_TSTATUS(i)));

	}

	/* Turn all the tiling regions off. */

	for (i = 0; i < NV10_PFB_TILE__SIZE; i++)

		nv10_graph_set_region_tiling(dev, i, 0, 0, 0);



	nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000);

	nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000);