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Commit cab3a802 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
Browse files

mmc: dw_mmc: clarify DDR timing mode between SD-UHS and eMMC 



Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50
is removed because of non-implementation of UHS signaling.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Acked-by: default avatarJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 1a0ae377

drivers/mmc/host/dw_mmc-exynos.c

+2 −3
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) 
	unsigned long actual;

	u8 div = priv->ciu_div + 1;



	if (ios->timing == MMC_TIMING_UHS_DDR50) {

	if (ios->timing == MMC_TIMING_MMC_DDR52) {

		mci_writel(host, CLKSEL, priv->ddr_timing);

		/* Should be double rate for DDR mode */

		if (ios->bus_width == MMC_BUS_WIDTH_8)
@@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode, 


/* Common capabilities of Exynos4/Exynos5 SoC */

static unsigned long exynos_dwmmc_caps[4] = {

	MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |

		MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,

	MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,

	MMC_CAP_CMD23,

	MMC_CAP_CMD23,

	MMC_CAP_CMD23,

drivers/mmc/host/dw_mmc.c

+1 −1
Original line number Diff line number Diff line
@@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
	regs = mci_readl(slot->host, UHS_REG);



	/* DDR mode set */

	if (ios->timing == MMC_TIMING_UHS_DDR50)

	if (ios->timing == MMC_TIMING_MMC_DDR52)

		regs |= ((0x1 << slot->id) << 16);

	else

		regs &= ~((0x1 << slot->id) << 16);