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Commit 1a0ae377 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
Browse files

mmc: rtsx: clarify DDR timing mode between SD-UHS and eMMC 



Added MMC_DDR52 as eMMC's DDR mode is distinguished from SD-UHS.

CC: Wei WANG <wei_wang@realsil.com.cn>
CC: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 4039ff47

drivers/mmc/host/rtsx_pci_sdmmc.c

+2 −0
Original line number Diff line number Diff line
@@ -1075,6 +1075,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);

		break;



	case MMC_TIMING_MMC_DDR52:

	case MMC_TIMING_UHS_DDR50:

		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,

				0x0C | SD_ASYNC_FIFO_NOT_RST,
@@ -1155,6 +1156,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
		host->vpclk = true;

		host->double_clk = false;

		break;

	case MMC_TIMING_MMC_DDR52:

	case MMC_TIMING_UHS_DDR50:

	case MMC_TIMING_UHS_SDR25:

		host->ssc_depth = RTSX_SSC_DEPTH_1M;