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Commit 4039ff47 authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
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mmc: sh_mmcif: clarify DDR timing mode between SD-UHS and eMMC 



Replaced UHS_DDR50 with MMC_DDR52.

CC: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 5438ad95

drivers/mmc/host/sh_mmcif.c

+5 −4
Original line number Diff line number Diff line
@@ -803,12 +803,13 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 
			break;

		}

		switch (host->timing) {

		case MMC_TIMING_UHS_DDR50:

		case MMC_TIMING_MMC_DDR52:

			/*

			 * MMC core will only set this timing, if the host

			 * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF

			 * implementations with this capability, e.g. sh73a0,

			 * will have to set it in their platform data.

			 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR

			 * capability. MMCIF implementations with this

			 * capability, e.g. sh73a0, will have to set it

			 * in their platform data.

			 */

			tmp |= CMD_SET_DARS;

			break;