ixgbe: Add check for FW veto bit (c97506ab) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+14 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************

	Intel 10 Gigabit PCI Express Linux driver		Intel 10 Gigabit PCI Express Linux driver
	Copyright(c) 1999 - 2013 Intel Corporation.		Copyright(c) 1999 - 2014 Intel Corporation.

	This program is free software; you can redistribute it and/or modify it		This program is free software; you can redistribute it and/or modify it
	under the terms and conditions of the GNU General Public License,		under the terms and conditions of the GNU General Public License,
	@@ -233,6 +233,10 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
	{		{
	s32 ret_val = 0;		s32 ret_val = 0;

			/* Blocked by MNG FW so bail */
			if (ixgbe_check_reset_blocked(hw))
			goto out;

	/* We only need to get the lock if:		/* We only need to get the lock if:
	* - We didn't do it already (in the read part of a read-modify-write)		* - We didn't do it already (in the read part of a read-modify-write)
	* - LESM is enabled.		* - LESM is enabled.
	@@ -247,6 +251,7 @@ static s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
	ret_val = ixgbe_reset_pipeline_82599(hw);		ret_val = ixgbe_reset_pipeline_82599(hw);

			out:
	/* Free the SW/FW semaphore as we either grabbed it here or		/* Free the SW/FW semaphore as we either grabbed it here or
	* already had it when this function was called.		* already had it when this function was called.
	*/		*/
	@@ -591,6 +596,10 @@ static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
	{		{
	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);		u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);

			/* Blocked by MNG FW so bail */
			if (ixgbe_check_reset_blocked(hw))
			return;

	/* Disable tx laser; allow 100us to go dark per spec */		/* Disable tx laser; allow 100us to go dark per spec */
	esdp_reg \|= IXGBE_ESDP_SDP3;		esdp_reg \|= IXGBE_ESDP_SDP3;
	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
	@@ -631,6 +640,10 @@ static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
	**/		**/
	static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)		static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
	{		{
			/* Blocked by MNG FW so bail */
			if (ixgbe_check_reset_blocked(hw))
			return;

	if (hw->mac.autotry_restart) {		if (hw->mac.autotry_restart) {
	ixgbe_disable_tx_laser_multispeed_fiber(hw);		ixgbe_disable_tx_laser_multispeed_fiber(hw);
	ixgbe_enable_tx_laser_multispeed_fiber(hw);		ixgbe_enable_tx_laser_multispeed_fiber(hw);

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

+43 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************

	Intel 10 Gigabit PCI Express Linux driver		Intel 10 Gigabit PCI Express Linux driver
	Copyright(c) 1999 - 2013 Intel Corporation.		Copyright(c) 1999 - 2014 Intel Corporation.

	This program is free software; you can redistribute it and/or modify it		This program is free software; you can redistribute it and/or modify it
	under the terms and conditions of the GNU General Public License,		under the terms and conditions of the GNU General Public License,
	@@ -97,6 +97,32 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
	return status;		return status;
	}		}

			/**
			* ixgbe_check_reset_blocked - check status of MNG FW veto bit
			* @hw: pointer to the hardware structure
			*
			* This function checks the MMNGC.MNG_VETO bit to see if there are
			* any constraints on link from manageability. For MAC's that don't
			* have this bit just return false since the link can not be blocked
			* via this method.
			**/
			s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
			{
			u32 mmngc;

			/* If we don't have this bit, it can't be blocking */
			if (hw->mac.type == ixgbe_mac_82598EB)
			return false;

			mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
			if (mmngc & IXGBE_MMNGC_MNG_VETO) {
			hw_dbg(hw, "MNG_VETO bit detected.\n");
			return true;
			}

			return false;
			}

	/**		/**
	* ixgbe_get_phy_id - Get the phy type		* ixgbe_get_phy_id - Get the phy type
	* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
	@@ -172,6 +198,10 @@ s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
	(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))		(IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
	goto out;		goto out;

			/* Blocked by MNG FW so bail */
			if (ixgbe_check_reset_blocked(hw))
			goto out;

	/*		/*
	* Perform soft PHY reset to the PHY_XS.		* Perform soft PHY reset to the PHY_XS.
	* This will cause a soft reset to the PHY		* This will cause a soft reset to the PHY
	@@ -476,6 +506,10 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
	autoneg_reg);		autoneg_reg);
	}		}

			/* Blocked by MNG FW so don't reset PHY */
			if (ixgbe_check_reset_blocked(hw))
			return status;

	/* Restart PHY autonegotiation and wait for completion */		/* Restart PHY autonegotiation and wait for completion */
	hw->phy.ops.read_reg(hw, MDIO_CTRL1,		hw->phy.ops.read_reg(hw, MDIO_CTRL1,
	MDIO_MMD_AN, &autoneg_reg);		MDIO_MMD_AN, &autoneg_reg);
	@@ -682,6 +716,10 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
	autoneg_reg);		autoneg_reg);
	}		}

			/* Blocked by MNG FW so don't reset PHY */
			if (ixgbe_check_reset_blocked(hw))
			return status;

	/* Restart PHY autonegotiation and wait for completion */		/* Restart PHY autonegotiation and wait for completion */
	hw->phy.ops.read_reg(hw, MDIO_CTRL1,		hw->phy.ops.read_reg(hw, MDIO_CTRL1,
	MDIO_MMD_AN, &autoneg_reg);		MDIO_MMD_AN, &autoneg_reg);
	@@ -759,6 +797,10 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
	s32 ret_val = 0;		s32 ret_val = 0;
	u32 i;		u32 i;

			/* Blocked by MNG FW so bail */
			if (ixgbe_check_reset_blocked(hw))
			goto out;

	hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);		hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);

	/* reset the PHY and poll for completion */		/* reset the PHY and poll for completion */

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************

	Intel 10 Gigabit PCI Express Linux driver		Intel 10 Gigabit PCI Express Linux driver
	Copyright(c) 1999 - 2013 Intel Corporation.		Copyright(c) 1999 - 2014 Intel Corporation.

	This program is free software; you can redistribute it and/or modify it		This program is free software; you can redistribute it and/or modify it
	under the terms and conditions of the GNU General Public License,		under the terms and conditions of the GNU General Public License,
	@@ -131,6 +131,7 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
	s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,		s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
	ixgbe_link_speed *speed,		ixgbe_link_speed *speed,
	bool *autoneg);		bool *autoneg);
			s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);

	/* PHY specific */		/* PHY specific */
	s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,		s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

+4 −1

Original line number	Original line	Diff line number	Diff line
	/*******************************************************************************		/*******************************************************************************

	Intel 10 Gigabit PCI Express Linux driver		Intel 10 Gigabit PCI Express Linux driver
	Copyright(c) 1999 - 2013 Intel Corporation.		Copyright(c) 1999 - 2014 Intel Corporation.

	This program is free software; you can redistribute it and/or modify it		This program is free software; you can redistribute it and/or modify it
	under the terms and conditions of the GNU General Public License,		under the terms and conditions of the GNU General Public License,
	@@ -1610,6 +1610,9 @@ enum {
	#define IXGBE_MACC_FS 0x00040000		#define IXGBE_MACC_FS 0x00040000
	#define IXGBE_MAC_RX2TX_LPBK 0x00000002		#define IXGBE_MAC_RX2TX_LPBK 0x00000002

			/* Veto Bit definiton */
			#define IXGBE_MMNGC_MNG_VETO 0x00000001

	/* LINKS Bit Masks */		/* LINKS Bit Masks */
	#define IXGBE_LINKS_KX_AN_COMP 0x80000000		#define IXGBE_LINKS_KX_AN_COMP 0x80000000
	#define IXGBE_LINKS_UP 0x40000000		#define IXGBE_LINKS_UP 0x40000000