Loading drivers/video/msm/mdss/mdss_mdp.c +5 −1 Original line number Diff line number Diff line Loading @@ -1400,7 +1400,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->hflip_buffer_reused = true; /* prevent disable of prefill calculations */ mdata->min_prefill_lines = 0xffff; /* clock gating feature is disabled by default */ /* clock gating feature is enabled by default */ mdata->enable_gate = true; mdata->pixel_ram_size = 0; Loading Loading @@ -1462,6 +1462,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); break; case MDSS_MDP_HW_REV_114: /* disable ECG for 28nm PHY platform */ mdata->enable_gate = false; case MDSS_MDP_HW_REV_116: mdata->max_target_zorder = 4; /* excluding base layer */ mdata->max_cursor_size = 128; Loading @@ -1488,6 +1490,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->pixel_ram_size = 16 * 1024; mdata->apply_post_scale_bytes = false; mdata->hflip_buffer_reused = false; /* disable ECG for 28nm PHY platform */ mdata->enable_gate = false; set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); set_bit(MDSS_QOS_PER_PIPE_LUT, mdata->mdss_qos_map); set_bit(MDSS_QOS_SIMPLIFIED_PREFILL, mdata->mdss_qos_map); Loading Loading
drivers/video/msm/mdss/mdss_mdp.c +5 −1 Original line number Diff line number Diff line Loading @@ -1400,7 +1400,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->hflip_buffer_reused = true; /* prevent disable of prefill calculations */ mdata->min_prefill_lines = 0xffff; /* clock gating feature is disabled by default */ /* clock gating feature is enabled by default */ mdata->enable_gate = true; mdata->pixel_ram_size = 0; Loading Loading @@ -1462,6 +1462,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map); break; case MDSS_MDP_HW_REV_114: /* disable ECG for 28nm PHY platform */ mdata->enable_gate = false; case MDSS_MDP_HW_REV_116: mdata->max_target_zorder = 4; /* excluding base layer */ mdata->max_cursor_size = 128; Loading @@ -1488,6 +1490,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->pixel_ram_size = 16 * 1024; mdata->apply_post_scale_bytes = false; mdata->hflip_buffer_reused = false; /* disable ECG for 28nm PHY platform */ mdata->enable_gate = false; set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map); set_bit(MDSS_QOS_PER_PIPE_LUT, mdata->mdss_qos_map); set_bit(MDSS_QOS_SIMPLIFIED_PREFILL, mdata->mdss_qos_map); Loading