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Commit 70b4e533 authored by Sandeep Panda's avatar Sandeep Panda
Browse files

msm: mdss: disable ECG feature on 28nm PHY platform 



On platform which use 28nm DSI PHY PLL, reconfiguring DSI
clocks as part of Early Clock Gating feature takes significant
time which in turn is causing power regressions. So disable
ECG feature on those platforms.

Change-Id: I41df9dd46138c472606c4479b14a225346816038
Signed-off-by: default avatarSandeep Panda <spanda@codeaurora.org>
parent 17d7bd58

drivers/video/msm/mdss/mdss_mdp.c

+5 −1
Original line number Diff line number Diff line
@@ -1361,7 +1361,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 
	mdata->hflip_buffer_reused = true;

	/* prevent disable of prefill calculations */

	mdata->min_prefill_lines = 0xffff;

	/* clock gating feature is disabled by default */

	/* clock gating feature is enabled by default */

	mdata->enable_gate = true;

	mdata->pixel_ram_size = 0;
@@ -1423,6 +1423,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 
		set_bit(MDSS_QOS_OTLIM, mdata->mdss_qos_map);

		break;

	case MDSS_MDP_HW_REV_114:

		/* disable ECG for 28nm PHY platform */

		mdata->enable_gate = false;

	case MDSS_MDP_HW_REV_116:

		mdata->max_target_zorder = 4; /* excluding base layer */

		mdata->max_cursor_size = 128;
@@ -1449,6 +1451,8 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) 
		mdata->pixel_ram_size = 16 * 1024;

		mdata->apply_post_scale_bytes = false;

		mdata->hflip_buffer_reused = false;

		/* disable ECG for 28nm PHY platform */

		mdata->enable_gate = false;

		set_bit(MDSS_QOS_CDP, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_PER_PIPE_LUT, mdata->mdss_qos_map);

		set_bit(MDSS_QOS_SIMPLIFIED_PREFILL, mdata->mdss_qos_map);