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Commit c6673cb5 authored by FUJITA Tomonori's avatar FUJITA Tomonori Committed by Chris Metcalf
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tile: set ARCH_KMALLOC_MINALIGN 



Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.

Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent 4b2bf4b3

arch/tile/include/asm/cache.h

+8 −0
Original line number Diff line number Diff line
@@ -31,6 +31,14 @@ 
#define L2_CACHE_BYTES		(1 << L2_CACHE_SHIFT)

#define L2_CACHE_ALIGN(x)	(((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)



/*

 * TILE-Gx is fully coherents so we don't need to define

 * ARCH_KMALLOC_MINALIGN.

 */

#ifndef __tilegx__

#define ARCH_KMALLOC_MINALIGN	L2_CACHE_BYTES

#endif



/* use the cache line size for the L2, which is where it counts */

#define SMP_CACHE_BYTES_SHIFT	L2_CACHE_SHIFT

#define SMP_CACHE_BYTES		L2_CACHE_BYTES