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Commit 4b2bf4b3 authored by FUJITA Tomonori's avatar FUJITA Tomonori Committed by Chris Metcalf
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tile: remove homegrown L1_CACHE_ALIGN macro 



Let's use the standard L1_CACHE_ALIGN macro instead.

Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent 0707ad30

arch/tile/include/asm/cache.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -20,7 +20,6 @@ 
/* bytes per L1 data cache line */

/* bytes per L1 data cache line */

#define L1_CACHE_SHIFT		CHIP_L1D_LOG_LINE_SIZE()

#define L1_CACHE_SHIFT		CHIP_L1D_LOG_LINE_SIZE()

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define L1_CACHE_ALIGN(x)	(((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)





/* bytes per L1 instruction cache line */

/* bytes per L1 instruction cache line */

#define L1I_CACHE_SHIFT		CHIP_L1I_LOG_LINE_SIZE()

#define L1I_CACHE_SHIFT		CHIP_L1I_LOG_LINE_SIZE()