Loading arch/arm/boot/dts/qcom/msm8996.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -2048,9 +2048,10 @@ phy_type= "utmi"; clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2phy_prim_reset>; <&clock_gcc clk_gcc_qusb2phy_prim_reset>, <&clock_gcc clk_ln_bb_clk>; clock-names = "cfg_ahb_clk", "phy_reset"; clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src"; }; qusb_phy1: qusb@7412000 { Loading Loading @@ -2083,9 +2084,10 @@ qcom,hold-reset; clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2phy_sec_reset>; <&clock_gcc clk_gcc_qusb2phy_sec_reset>, <&clock_gcc clk_ln_bb_clk>; clock-names = "cfg_ahb_clk", "phy_reset"; clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src"; }; ssphy: ssphy@7410000 { Loading Loading
arch/arm/boot/dts/qcom/msm8996.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -2048,9 +2048,10 @@ phy_type= "utmi"; clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2phy_prim_reset>; <&clock_gcc clk_gcc_qusb2phy_prim_reset>, <&clock_gcc clk_ln_bb_clk>; clock-names = "cfg_ahb_clk", "phy_reset"; clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src"; }; qusb_phy1: qusb@7412000 { Loading Loading @@ -2083,9 +2084,10 @@ qcom,hold-reset; clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2phy_sec_reset>; <&clock_gcc clk_gcc_qusb2phy_sec_reset>, <&clock_gcc clk_ln_bb_clk>; clock-names = "cfg_ahb_clk", "phy_reset"; clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src"; }; ssphy: ssphy@7410000 { Loading