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Commit 1bda927f authored by Jack Pham's avatar Jack Pham
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ARM: dts: msm: Add ref_clk_src to QUSB PHYs on msm8996 



The QUSB PHY instances each require a ref clk sourced by PMIC
ln_bb_clk in order to function properly. Since this clock is
shared among other peripherals, make sure the PHYs also can
enable it independently when needed.

Change-Id: Id5837532a2c9249b7babb720483c94734d80b717
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 7427cd00

arch/arm/boot/dts/qcom/msm8996.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -2033,9 +2033,10 @@ 
		phy_type= "utmi";



		clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			 <&clock_gcc clk_gcc_qusb2phy_prim_reset>;

			 <&clock_gcc clk_gcc_qusb2phy_prim_reset>,

			 <&clock_gcc clk_ln_bb_clk>;



		clock-names = "cfg_ahb_clk", "phy_reset";

		clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src";

	};



	qusb_phy1: qusb@7412000 {
@@ -2068,9 +2069,10 @@ 
		qcom,hold-reset;



		clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,

			 <&clock_gcc clk_gcc_qusb2phy_sec_reset>;

			 <&clock_gcc clk_gcc_qusb2phy_sec_reset>,

			 <&clock_gcc clk_ln_bb_clk>;



		clock-names = "cfg_ahb_clk", "phy_reset";

		clock-names = "cfg_ahb_clk", "phy_reset", "ref_clk_src";

	};



	ssphy: ssphy@7410000 {