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Commit c2b86fa6 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Move the secure region to 0xE8000000 



We can only have one secure region to rule them all and since legacy
and 32 bit applications need to have access to the region too, we
need to move it into the lower 32 bits.

Change-Id: Ic0dedbada6de060b2ac3d0c26e9ea91a833a16f8
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 2344e053

drivers/gpu/msm/adreno.c

+7 −18
Original line number Diff line number Diff line
@@ -1315,24 +1315,13 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
		adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_CONTROL, 0x0);



		if (ADRENO_FEATURE(adreno_dev, ADRENO_64BIT) &&

			MMU_FEATURE(&device->mmu, KGSL_MMU_64BIT)) {

		adreno_writereg64(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

				KGSL_IOMMU_SECURE_BASE64);

			KGSL_IOMMU_SECURE_BASE);

		adreno_writereg(adreno_dev,

			ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

				KGSL_IOMMU_SECURE_SIZE64);

		} else {

			adreno_writereg64(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,

				ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,

				KGSL_IOMMU_SECURE_BASE32);

			adreno_writereg(adreno_dev,

				ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,

				KGSL_IOMMU_SECURE_SIZE32);

		}

			KGSL_IOMMU_SECURE_SIZE);

	}



	status = adreno_ocmem_malloc(adreno_dev);

drivers/gpu/msm/kgsl_iommu.c

+5 −5
Original line number Diff line number Diff line
@@ -485,8 +485,8 @@ static void setup_64bit_pagetable(struct kgsl_mmu *mmu, 
		struct kgsl_iommu_pt *pt)

{

	if (mmu->secured && pagetable->name == KGSL_MMU_SECURE_PT) {

		pt->va_start = KGSL_IOMMU_SECURE_BASE64;

		pt->va_end = KGSL_IOMMU_SECURE_END64;

		pt->va_start = KGSL_IOMMU_SECURE_BASE;

		pt->va_end = KGSL_IOMMU_SECURE_END;

	} else {

		pt->compat_va_start = KGSL_IOMMU_SVM_BASE32;

		pt->compat_va_end = KGSL_IOMMU_SVM_END32;
@@ -512,11 +512,11 @@ static void setup_32bit_pagetable(struct kgsl_mmu *mmu, 
{

	if (mmu->secured) {

		if (pagetable->name == KGSL_MMU_SECURE_PT) {

			pt->va_start = KGSL_IOMMU_SECURE_BASE32;

			pt->va_end = KGSL_IOMMU_SECURE_END32;

			pt->va_start = KGSL_IOMMU_SECURE_BASE;

			pt->va_end = KGSL_IOMMU_SECURE_END;

		} else {

			pt->va_start = KGSL_IOMMU_SVM_BASE32;

			pt->va_end = KGSL_IOMMU_SECURE_BASE32;

			pt->va_end = KGSL_IOMMU_SECURE_BASE;

			pt->compat_va_start = pt->va_start;

			pt->compat_va_end = pt->va_end;

		}

drivers/gpu/msm/kgsl_iommu.h

+4 −10
Original line number Diff line number Diff line
@@ -19,20 +19,14 @@ 
#include <linux/of.h>

#include "kgsl.h"



#define KGSL_IOMMU_SECURE_SIZE32 SZ_256M

#define KGSL_IOMMU_SECURE_END32 KGSL_MMU_GLOBAL_MEM_BASE

#define KGSL_IOMMU_SECURE_BASE32	\

	(KGSL_MMU_GLOBAL_MEM_BASE - KGSL_IOMMU_SECURE_SIZE32)

#define KGSL_IOMMU_SECURE_SIZE SZ_256M

#define KGSL_IOMMU_SECURE_END KGSL_MMU_GLOBAL_MEM_BASE

#define KGSL_IOMMU_SECURE_BASE	\

	(KGSL_MMU_GLOBAL_MEM_BASE - KGSL_IOMMU_SECURE_SIZE)



#define KGSL_IOMMU_SVM_BASE32		0x300000

#define KGSL_IOMMU_SVM_END32		(0xC0000000 - SZ_16M)



#define KGSL_IOMMU_SECURE_BASE64	0x300000000ULL

/* this size is a hardware enforced maximum */

#define KGSL_IOMMU_SECURE_SIZE64	0x0FFFFF000ULL

#define KGSL_IOMMU_SECURE_END64 \

	(KGSL_IOMMU_SECURE_BASE64 + KGSL_IOMMU_SECURE_SIZE64)



#define KGSL_IOMMU_VA_BASE64		0x500000000ULL

#define KGSL_IOMMU_VA_END64		0x600000000ULL

/*