Merge "mmc: sdhci-msm: Enable one MID for SDHCI controller" (2344e053) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/mmc/host/sdhci-msm.c

+15 −0

Original line number	Diff line number	Diff line
		@@ -118,6 +118,9 @@
		#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114
		#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118

		#define CORE_VENDOR_SPEC_FUNC2 0x110
		#define CORE_ONE_MID_EN (1 << 25)

		#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11C
		#define CORE_8_BIT_SUPPORT (1 << 18)
		#define CORE_3_3V_SUPPORT (1 << 24)
		@@ -2760,6 +2763,8 @@ void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
		readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC),
		readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR0),
		readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_ADMA_ERR_ADDR1));
		pr_info("Vndr func2: 0x%08x\n",
		readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_FUNC2));

		/*
		* tbsel indicates [2:0] bits and tbsel2 indicates [7:4] bits
		@@ -2917,6 +2922,7 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
		u32 version, caps = 0;
		u16 minor;
		u8 major;
		u32 val;

		version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
		major = (version & CORE_VERSION_MAJOR_MASK) >>
		@@ -2945,6 +2951,15 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host,
		caps \|= CORE_8_BIT_SUPPORT;
		}

		/*
		* Enable one MID mode for SDCC5 (major 1) on 8916/8939 (minor 0x2e) and
		* on 8992 (minor 0x3e) as a workaround to reset for data stuck issue.
		*/
		if (major == 1 && (minor == 0x2e \|\| minor == 0x3e)) {
		val = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC_FUNC2);
		writel_relaxed((val \| CORE_ONE_MID_EN),
		host->ioaddr + CORE_VENDOR_SPEC_FUNC2);
		}
		/*
		* SDCC 5 controller with major version 1, minor version 0x34 and later
		* with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.