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Commit c1858123 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Enable CB tuning of the Display PLL 



Magic numbers from the specs. This is supposed to allow the PLL some
variance to improve jitter performance and VCO headroom across
manufacturing and environmental variations.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent a589b9f4

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -2712,6 +2712,7 @@ 
#define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B)



#define PCH_FPA0                0xc6040

#define  FP_CB_TUNE		(0x3<<22)

#define PCH_FPA1                0xc6044

#define PCH_FPB0                0xc6048

#define PCH_FPB1                0xc604c

drivers/gpu/drm/i915/intel_display.c

+16 −1
Original line number Diff line number Diff line
@@ -3857,6 +3857,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, 
				reduced_clock.m2;

	}



	/* Enable autotuning of the PLL clock (if permissible) */

	if (HAS_PCH_SPLIT(dev)) {

		int factor = 21;



		if (is_lvds) {

			if ((dev_priv->lvds_use_ssc &&

			     dev_priv->lvds_ssc_freq == 100) ||

			    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)

				factor = 25;

		} else if (is_sdvo && is_tv)

			factor = 20;



		if (clock.m1 < factor * clock.n)

			fp |= FP_CB_TUNE;

	}



	dpll = 0;

	if (!HAS_PCH_SPLIT(dev))

		dpll = DPLL_VGA_MODE_DIS;
@@ -4071,7 +4087,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, 
	}



	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {

		I915_WRITE(fp_reg, fp);

		I915_WRITE(dpll_reg, dpll);



		/* Wait for the clocks to stabilize. */