Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a589b9f4 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Explain why we need to write DPLL twice 



... it's because setting the Pixel Multiply bits only takes effect once
the PLL is enabled and stable.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 17fe6981

drivers/gpu/drm/i915/intel_display.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -4089,13 +4089,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, 
			}

			}

			I915_WRITE(DPLL_MD(pipe), temp);

			I915_WRITE(DPLL_MD(pipe), temp);

		} else {

		} else {

			/* write it again -- the BIOS does, after all */

			/* The pixel multiplier can only be updated once the

			 * DPLL is enabled and the clocks are stable.

			 *

			 * So write it again.

			 */

			I915_WRITE(dpll_reg, dpll);

			I915_WRITE(dpll_reg, dpll);

		}

		}



		/* Wait for the clocks to stabilize. */

		POSTING_READ(dpll_reg);

		udelay(150);

	}

	}





	intel_crtc->lowfreq_avail = false;

	intel_crtc->lowfreq_avail = false;