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Commit bf852799 authored by Christian König's avatar Christian König Committed by Dave Airlie
Browse files

drm/radeon: make cp variable an array 



Replace cp, cp1 and cp2 members with just an array
of radeon_cp structs.

Signed-off-by: default avatarChristian König <deathsimple@vodafone.de>
Reviewed-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 5596a9db

drivers/gpu/drm/radeon/evergreen.c

+7 −7
Original line number Diff line number Diff line
@@ -1311,7 +1311,7 @@ void evergreen_mc_program(struct radeon_device *rdev) 
 */

void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[ib->fence->ring];



	/* set to DX10/11 mode */

	radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0));
@@ -1362,7 +1362,7 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) 


static int evergreen_cp_start(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r, i;

	uint32_t cp_me;
@@ -1428,7 +1428,7 @@ static int evergreen_cp_start(struct radeon_device *rdev) 


int evergreen_cp_resume(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 tmp;

	u32 rb_bufsz;

	int r;
@@ -3056,7 +3056,7 @@ restart_ih: 


static int evergreen_startup(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r;



	/* enable pcie gen2 link */
@@ -3168,7 +3168,7 @@ int evergreen_resume(struct radeon_device *rdev) 


int evergreen_suspend(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];



	/* FIXME: we should wait for ring to be empty */

	r700_cp_stop(rdev);
@@ -3251,8 +3251,8 @@ int evergreen_init(struct radeon_device *rdev) 
	if (r)

		return r;



	rdev->cp.ring_obj = NULL;

	r600_ring_init(rdev, &rdev->cp, 1024 * 1024);

	rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;

	r600_ring_init(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);



	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+8 −8
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ static void 
set_render_target(struct radeon_device *rdev, int format,

		  int w, int h, u64 gpu_addr)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 cb_color_info;

	int pitch, slice;
@@ -88,7 +88,7 @@ cp_set_surface_sync(struct radeon_device *rdev, 
		    u32 sync_type, u32 size,

		    u64 mc_addr)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 cp_coher_size;



	if (size == 0xffffffff)
@@ -116,7 +116,7 @@ cp_set_surface_sync(struct radeon_device *rdev, 
static void

set_shaders(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u64 gpu_addr;



	/* VS */
@@ -144,7 +144,7 @@ set_shaders(struct radeon_device *rdev) 
static void

set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 sq_vtx_constant_word2, sq_vtx_constant_word3;



	/* high addr, stride */
@@ -189,7 +189,7 @@ set_tex_resource(struct radeon_device *rdev, 
		 int format, int w, int h, int pitch,

		 u64 gpu_addr, u32 size)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 sq_tex_resource_word0, sq_tex_resource_word1;

	u32 sq_tex_resource_word4, sq_tex_resource_word7;
@@ -230,7 +230,7 @@ static void 
set_scissors(struct radeon_device *rdev, int x1, int y1,

	     int x2, int y2)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	/* workaround some hw bugs */

	if (x2 == 0)

		x1 = 1;
@@ -261,7 +261,7 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, 
static void

draw_auto(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));

	radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);

	radeon_ring_write(cp, DI_PT_RECTLIST);
@@ -286,7 +286,7 @@ draw_auto(struct radeon_device *rdev) 
static void

set_default_state(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;

	u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;

	u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;

drivers/gpu/drm/radeon/ni.c

+15 −15
Original line number Diff line number Diff line
@@ -1049,7 +1049,7 @@ static int cayman_cp_load_microcode(struct radeon_device *rdev) 


static int cayman_cp_start(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r, i;



	r = radeon_ring_lock(rdev, cp, 7);
@@ -1116,7 +1116,7 @@ static int cayman_cp_start(struct radeon_device *rdev) 
static void cayman_cp_fini(struct radeon_device *rdev)

{

	cayman_cp_enable(rdev, false);

	radeon_ring_fini(rdev, &rdev->cp);

	radeon_ring_fini(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);

}



int cayman_cp_resume(struct radeon_device *rdev)
@@ -1147,7 +1147,7 @@ int cayman_cp_resume(struct radeon_device *rdev) 


	/* ring 0 - compute and gfx */

	/* Set ring buffer size */

	cp = &rdev->cp;

	cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	rb_bufsz = drm_order(cp->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN
@@ -1181,7 +1181,7 @@ int cayman_cp_resume(struct radeon_device *rdev) 


	/* ring1  - compute only */

	/* Set ring buffer size */

	cp = &rdev->cp1;

	cp = &rdev->cp[CAYMAN_RING_TYPE_CP1_INDEX];

	rb_bufsz = drm_order(cp->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN
@@ -1207,7 +1207,7 @@ int cayman_cp_resume(struct radeon_device *rdev) 


	/* ring2 - compute only */

	/* Set ring buffer size */

	cp = &rdev->cp2;

	cp = &rdev->cp[CAYMAN_RING_TYPE_CP2_INDEX];

	rb_bufsz = drm_order(cp->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN
@@ -1233,15 +1233,15 @@ int cayman_cp_resume(struct radeon_device *rdev) 


	/* start the rings */

	cayman_cp_start(rdev);

	rdev->cp.ready = true;

	rdev->cp1.ready = true;

	rdev->cp2.ready = true;

	rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = true;

	rdev->cp[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;

	rdev->cp[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;

	/* this only test cp0 */

	r = radeon_ring_test(rdev, &rdev->cp);

	r = radeon_ring_test(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);

	if (r) {

		rdev->cp.ready = false;

		rdev->cp1.ready = false;

		rdev->cp2.ready = false;

		rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;

		rdev->cp[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;

		rdev->cp[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;

		return r;

	}
@@ -1343,7 +1343,7 @@ int cayman_asic_reset(struct radeon_device *rdev) 


static int cayman_startup(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r;



	/* enable pcie gen2 link */
@@ -1438,7 +1438,7 @@ int cayman_suspend(struct radeon_device *rdev) 
{

	/* FIXME: we should wait for ring to be empty */

	cayman_cp_enable(rdev, false);

	rdev->cp.ready = false;

	rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	evergreen_irq_suspend(rdev);

	radeon_wb_disable(rdev);

	cayman_pcie_gart_disable(rdev);
@@ -1455,7 +1455,7 @@ int cayman_suspend(struct radeon_device *rdev) 
 */

int cayman_init(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r;



	/* This don't do much */

drivers/gpu/drm/radeon/r100.c

+9 −9
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 
void r100_fence_ring_emit(struct radeon_device *rdev,

			  struct radeon_fence *fence)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[fence->ring];



	/* We have to make sure that caches are flushed before

	 * CPU might read something from VRAM. */
@@ -849,7 +849,7 @@ int r100_copy_blit(struct radeon_device *rdev, 
		   unsigned num_gpu_pages,

		   struct radeon_fence *fence)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	uint32_t cur_pages;

	uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;

	uint32_t pitch;
@@ -934,7 +934,7 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev) 


void r100_ring_start(struct radeon_device *rdev)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	int r;



	r = radeon_ring_lock(rdev, cp, 2);
@@ -1048,7 +1048,7 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) 


int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	unsigned rb_bufsz;

	unsigned rb_blksz;

	unsigned max_fetch;
@@ -1162,7 +1162,7 @@ void r100_cp_fini(struct radeon_device *rdev) 
	}

	/* Disable ring */

	r100_cp_disable(rdev);

	radeon_ring_fini(rdev, &rdev->cp);

	radeon_ring_fini(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);

	DRM_INFO("radeon: cp finalized\n");

}
@@ -1170,7 +1170,7 @@ void r100_cp_disable(struct radeon_device *rdev) 
{

	/* Disable ring */

	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);

	rdev->cp.ready = false;

	rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	WREG32(RADEON_CP_CSQ_MODE, 0);

	WREG32(RADEON_CP_CSQ_CNTL, 0);

	WREG32(R_000770_SCRATCH_UMSK, 0);
@@ -2587,7 +2587,7 @@ static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 
	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	uint32_t rdp, wdp;

	unsigned count, i, j;
@@ -3686,7 +3686,7 @@ int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp) 


void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];



	radeon_ring_write(cp, PACKET0(RADEON_CP_IB_BASE, 1));

	radeon_ring_write(cp, ib->gpu_addr);
@@ -3778,7 +3778,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 
	/* Shutdown CP we shouldn't need to do that but better be safe than

	 * sorry

	 */

	rdev->cp.ready = false;

	rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;

	WREG32(R_000740_CP_CSQ_CNTL, 0);



	/* Save few CRTC registers */

drivers/gpu/drm/radeon/r200.c

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ int r200_copy_dma(struct radeon_device *rdev, 
		  unsigned num_gpu_pages,

		  struct radeon_fence *fence)

{

	struct radeon_cp *cp = &rdev->cp;

	struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];

	uint32_t size;

	uint32_t cur_size;

	int i, num_loops;