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Commit b9e1faa7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ 



The bit controlling whether PIPE_CONTROL DW/QW write targets
the global GTT or PPGTT moved moved from DW 2 bit 2 to
DW 1 bit 24 on IVB.

I verified on IVB that the fix is in fact effective. Without the fix
none of the scratch writes actually landed in the pipe control page.
With the fix the writes show up correctly.

v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 4f7dfb67

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -308,6 +308,7 @@ 
#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */

#define   PIPE_CONTROL_CS_STALL				(1<<20)

#define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)

#define   PIPE_CONTROL_QW_WRITE				(1<<14)

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −1
Original line number Diff line number Diff line
@@ -318,6 +318,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, 
		 * TLB invalidate requires a post-sync write.

		 */

		flags |= PIPE_CONTROL_QW_WRITE;

		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;



		/* Workaround: we must issue a pipe_control with CS-stall bit

		 * set before a pipe_control command that has the state cache
@@ -331,7 +332,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, 


	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));

	intel_ring_emit(ring, flags);

	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, scratch_addr);

	intel_ring_emit(ring, 0);

	intel_ring_advance(ring);