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Commit 4f7dfb67 authored by Patrik Jakobsson's avatar Patrik Jakobsson Committed by Daniel Vetter
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drm/i915: Set i9xx sdvo clock limits according to specifications 



The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: default avatarPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359


Cc: stable@vger.kernel.org
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 53a7d2d1

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -154,8 +154,8 @@ static const intel_limit_t intel_limits_i9xx_sdvo = { 
	.vco = { .min = 1400000, .max = 2800000 },

	.n = { .min = 1, .max = 6 },

	.m = { .min = 70, .max = 120 },

	.m1 = { .min = 10, .max = 22 },

	.m2 = { .min = 5, .max = 9 },

	.m1 = { .min = 8, .max = 18 },

	.m2 = { .min = 3, .max = 7 },

	.p = { .min = 5, .max = 80 },

	.p1 = { .min = 1, .max = 8 },

	.p2 = { .dot_limit = 200000,