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Commit b88b1cc7 authored by Changhwan Youn's avatar Changhwan Youn Committed by Kukjin Kim
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ARM: EXYNOS4: Add support clock for EXYNOS4412 



This patch makes EXYNOS4412 use same clock code for
EXYNOS4212 because the clock hierarchy of both SoCs
are same.

Signed-off-by: default avatarChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent e6a275a8

arch/arm/mach-exynos4/clock.c

+2 −2
Original line number Diff line number Diff line
@@ -1149,7 +1149,7 @@ static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 
	if (soc_is_exynos4210())

		return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),

					pll_4508);

	else if (soc_is_exynos4212())

	else if (soc_is_exynos4212() || soc_is_exynos4412())

		return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));

	else

		return 0;
@@ -1200,7 +1200,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) 
		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);

		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),

					__raw_readl(S5P_VPLL_CON1), pll_4650c);

	} else if (soc_is_exynos4212()) {

	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {

		apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));

		mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));

		epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),