Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e6a275a8 authored by Changhwan Youn's avatar Changhwan Youn Committed by Kukjin Kim
Browse files

ARM: EXYNOS4: Add support new EXYNOS4412 SoC 



This patch adds Samsung EXYNOS4412 SoC support.
The EXYNOS4412 integrates a ARM Cortex A9 quad-core.

Signed-off-by: default avatarChanghwan Youn <chaos.youn@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 3a062281

arch/arm/mach-exynos4/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -20,6 +20,11 @@ config SOC_EXYNOS4212 
	help

	  Enable EXYNOS4212 SoC support



config SOC_EXYNOS4412

	bool

	help

	  Enable EXYNOS4412 SoC support



config EXYNOS4_MCT

	bool

	default y

arch/arm/mach-exynos4/cpu.c

+2 −2
Original line number Diff line number Diff line
@@ -191,7 +191,7 @@ void __init exynos4_init_clocks(int xtal) 


	if (soc_is_exynos4210())

		exynos4210_register_clocks();

	else if (soc_is_exynos4212())

	else if (soc_is_exynos4212() || soc_is_exynos4412())

		exynos4212_register_clocks();



	exynos4_register_clocks();
@@ -255,7 +255,7 @@ static int __init exynos4_l2x0_cache_init(void) 


	if (soc_is_exynos4210())

		__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);

	else if (soc_is_exynos4212())

	else if (soc_is_exynos4212() || soc_is_exynos4412())

		__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);



	/* L2X0 Prefetch Control */

arch/arm/plat-s5p/cpu.c

+9 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ static const char name_s5pc100[] = "S5PC100"; 
static const char name_s5pv210[] = "S5PV210/S5PC110";

static const char name_exynos4210[] = "EXYNOS4210";

static const char name_exynos4212[] = "EXYNOS4212";

static const char name_exynos4412[] = "EXYNOS4412";



static struct cpu_table cpu_ids[] __initdata = {

	{
@@ -84,6 +85,14 @@ static struct cpu_table cpu_ids[] __initdata = { 
		.init_uarts	= exynos4_init_uarts,

		.init		= exynos4_init,

		.name		= name_exynos4212,

	}, {

		.idcode		= EXYNOS4412_CPU_ID,

		.idmask		= EXYNOS4_CPU_MASK,

		.map_io		= exynos4_map_io,

		.init_clocks	= exynos4_init_clocks,

		.init_uarts	= exynos4_init_uarts,

		.init		= exynos4_init,

		.name		= name_exynos4412,

	},

};

arch/arm/plat-samsung/include/plat/cpu.h

+8 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ extern unsigned long samsung_cpu_id; 


#define EXYNOS4210_CPU_ID	0x43210000

#define EXYNOS4212_CPU_ID	0x43220000

#define EXYNOS4412_CPU_ID	0xE4412200

#define EXYNOS4_CPU_MASK	0xFFFE0000



#define IS_SAMSUNG_CPU(name, id, mask)		\
@@ -56,6 +57,7 @@ IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) 
IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)

IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)

IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)

IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)



#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \

    defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -108,6 +110,12 @@ IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) 
# define soc_is_exynos4212()	0

#endif



#if defined(CONFIG_SOC_EXYNOS4412)

# define soc_is_exynos4412()	is_samsung_exynos4412()

#else

# define soc_is_exynos4412()	0

#endif



#define EXYNOS4210_REV_0	(0x0)

#define EXYNOS4210_REV_1_0	(0x10)

#define EXYNOS4210_REV_1_1	(0x11)