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Commit b74ea102 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: IVB FBC WaFbcDisableDpfcClockGating 



Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
v4: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 30ca7c6f

drivers/gpu/drm/i915/intel_pm.c

+11 −0
Original line number Diff line number Diff line
@@ -242,6 +242,12 @@ static void ironlake_disable_fbc(struct drm_device *dev) 
		dpfc_ctl &= ~DPFC_CTL_EN;

		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);



		if (IS_IVYBRIDGE(dev))

			/* WaFbcDisableDpfcClockGating */

			I915_WRITE(ILK_DSPCLK_GATE_D,

				   I915_READ(ILK_DSPCLK_GATE_D) &

				   ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);



		DRM_DEBUG_KMS("disabled FBC\n");

	}

}
@@ -270,6 +276,11 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 


	/* WaFbcAsynchFlipDisableFbcQueue */

	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);

	/* WaFbcDisableDpfcClockGating */

	I915_WRITE(ILK_DSPCLK_GATE_D,

		   I915_READ(ILK_DSPCLK_GATE_D) |

		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE);



	I915_WRITE(SNB_DPFC_CTL_SA,

		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);

	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);