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Commit 30ca7c6f authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue 



Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent abe959c7

drivers/gpu/drm/i915/intel_pm.c

+2 −0
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		   IVB_DPFC_CTL_FENCE_EN |

		   intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);



	/* WaFbcAsynchFlipDisableFbcQueue */

	I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);

	I915_WRITE(SNB_DPFC_CTL_SA,

		   SNB_CPU_FENCE_ENABLE | obj->fence_reg);

	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);