Commit b6d116c9 authored Mar 03, 2016 by Taniya Das

clk: msm: gcc: Update config ctl value for GPLL3



The MIN_GLITCH_THRESHOLD value for gpll3 needs to be set, update the config
ctl value to reflect the same.

CRs-Fixed: 984845
Change-Id: Ib32a7dbbd0d27042e648bbf4f3e3c0c44368d40b
Signed-off-by: Taniya Das <tdas@codeaurora.org>

parent 2ba7432c

drivers/clk/msm/clock-gcc-8953.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -161,7 +161,7 @@ static struct alpha_pll_clk gpll3_clk_src = {
		.enable_config = 1,
		.post_div_config = 1 << 8,
		.slew = true,
		.config_ctl_val = 0x4001051b,
		.config_ctl_val = 0x4001055b,
		.c = {
		.rate = 1300000000,
		.parent = &xo_clk_src.c,