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Commit b4d1601b authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: add coresight components for subsystems for msmthorium 



Add CoreSight components like CPU CTIs, ETMs for retmoe subsystems.

Change-Id: Ib9c9e26b55b2f398d77587d4fd4b6d05062bcb9d
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 0600f6c1

arch/arm/boot/dts/qcom/msmthorium-coresight.dtsi

+115 −2
Original line number Original line Diff line number Diff line
@@ -677,12 +677,125 @@ 
		clock-names = "core_clk", "core_a_clk";

		clock-names = "core_clk", "core_a_clk";

	};

	};





	cti_modem_cpu0: cti@6124000 {

		compatible = "arm,coresight-cti";

		reg = <0x6124000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <42>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Proto CTI */

	cti_wcn_cpu0: cti@6139000 {

		compatible = "arm,coresight-cti";

		reg = <0x6139000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <43>;

		coresight-name = "coresight-cti-wcn-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Venus CTI */

	cti_video_cpu0: cti@6134000 {

		compatible = "arm,coresight-cti";

		reg = <0x6134000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <44>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* LPASS CTI */

	cti_audio_cpu0: cti@613c000 {

		compatible = "arm,coresight-cti";

		reg = <0x613c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <45>;

		coresight-name = "coresight-cti-audio-cpu0";

		coresight-nr-inports = <0>;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	/* Proto ETM */

	wcn_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <46>;

		coresight-name = "coresight-wcn-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <0>;



		qcom,inst-id = <3>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <47>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_center>;

		coresight-child-ports = <0>;



		qcom,inst-id = <4>;

	};



	/* LPASS ETM */

	audio_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <48>;

		coresight-name = "coresight-audio-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_mm>;

		coresight-child-ports = <5>;



		qcom,inst-id = <5>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-id = <49>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_right>;

		coresight-child-ports = <1>;



		qcom,inst-id = <2>;

	};



	csr: csr@6001000 {

	csr: csr@6001000 {

		compatible = "qcom,coresight-csr";

		compatible = "qcom,coresight-csr";

		reg = <0x6001000 0x1000>;

		reg = <0x6001000 0x1000>;

		reg-names = "csr-base";

		reg-names = "csr-base";





		coresight-id = <42>;

		coresight-id = <50>;

		coresight-name = "coresight-csr";

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;

		qcom,blk-size = <1>;
@@ -697,7 +810,7 @@ 
		reg = <0x6108000 0x1000>;

		reg = <0x6108000 0x1000>;

		reg-names = "dbgui-base";

		reg-names = "dbgui-base";





		coresight-id = <43>;

		coresight-id = <51>;

		coresight-name = "coresight-dbgui";

		coresight-name = "coresight-dbgui";

		coresight-nr-inports = <0>;

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-outports = <0>;