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Commit 0600f6c1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable gcc clock driver for mdmfermium clocks"

parents aad71452 2e0e656e

Documentation/devicetree/bindings/arm/msm/clock-controller.txt

+2 −0
Original line number Diff line number Diff line
@@ -52,6 +52,8 @@ Required properties: 
			"qcom,gpucc-8996-v3.0"

			"qcom,gcc-californium"

			"qcom,cc-debug-californium"

			"qcom,gcc-mdmfermium"

			"qcom,cc-debug-mdmfermium"



- reg:			Pairs of physical base addresses and region sizes of

			memory mapped registers.

arch/arm/boot/dts/qcom/mdmfermium.dtsi

+7 −2
Original line number Diff line number Diff line
@@ -158,12 +158,17 @@ 
	};



	clock_gcc: qcom,gcc@1800000 {

		compatible = "qcom,dummycc";

		compatible = "qcom,gcc-mdmfermium";

		reg = <0x1800000 0x80000>;

		reg-names = "cc_base";

		vdd_dig-supply = <&mdmfermium_s3_level>;

		#clock-cells = <1>;

	};



	clock_debug: qcom,debug@1874000 {

		compatible = "qcom,dummycc";

		compatible = "qcom,cc-debug-mdmfermium";

		reg = <0x1800000 0x80000>;

		reg-names = "cc_base";

		#clock-cells = <1>;

	};

drivers/clk/msm/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -19,6 +19,9 @@ obj-$(CONFIG_ARCH_MSM8996) += clock-cpu-8996.o 
# MDMCALIFORNIUM

obj-$(CONFIG_ARCH_MDMCALIFORNIUM)	+= clock-gcc-californium.o



# MDMFERMIUM

obj-$(CONFIG_ARCH_MDMFERMIUM)	+=clock-gcc-mdmfermium.o



# ACPU clock

obj-$(CONFIG_ARCH_MDM9640)      += clock-a7.o

obj-$(CONFIG_ARCH_MDMCALIFORNIUM)	+= clock-a7.o

drivers/clk/msm/clock-gcc-mdmfermium.c

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+1744 −0

File added.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/mdm-clocks-fermium.h

+2 −7
Original line number Diff line number Diff line
@@ -44,12 +44,6 @@ 
#define clk_xo_pil_mss_clk					 0xe97a8354

#define clk_bb_clk1						 0xf5304268

#define clk_bb_clk1_pin						 0x6dd0a779

#define clk_bb_clk2						 0xfe15cb87

#define clk_bb_clk2_pin						 0x498938e5

#define clk_rf_clk1						 0xaabeea5a

#define clk_rf_clk1_pin						 0x8f463562

#define clk_rf_clk2						 0x24a30992

#define clk_rf_clk2_pin						 0xa7c5602a



/* SRCs */

#define clk_apss_ahb_clk_src					 0x36f8495f
@@ -142,7 +136,8 @@ 
#define clk_gcc_usb_hsic_io_cal_clk				 0xbc21f776

#define clk_gcc_usb_hsic_io_cal_sleep_clk			 0x20e09a22

#define clk_gcc_usb_hsic_system_clk				 0x145e9366



#define clk_gcc_usb2_hs_phy_only_clk				 0x0047179d

#define clk_gcc_qusb2_phy_clk					 0x996884d5

/* DEBUG */

#define clk_gcc_debug_mux					 0x8121ac15

#define clk_wcnss_m_clk						 0x709f430b