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Commit b3c35110 authored by Mukesh Kumar Savaliya's avatar Mukesh Kumar Savaliya
Browse files

ARM: dts: msm: specify UART configuration for APQ8017 



APQ8017 has Bluetooth use case on UART1, hence populate dtsi
with UART1 instance support.

Change-Id: Iaef470317b92bd1b9a13140d6a97282c48f2f7f4
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent 64120cd2

arch/arm/boot/dts/qcom/apq8017-pmi8937-cdp-wcd-rome.dts

+4 −0
Original line number Diff line number Diff line
@@ -23,3 +23,7 @@ 
	qcom,board-id= <1 2>;

	qcom,pmic-id = <0x10019 0x020037 0x0 0x0>;

};



&blsp1_uart1 {

	status = "ok";

};

arch/arm/boot/dts/qcom/apq8017-pmi8950-cdp-wcd-rome.dts

+4 −0
Original line number Diff line number Diff line
@@ -23,3 +23,7 @@ 
	qcom,board-id= <1 2>;

	qcom,pmic-id = <0x10019 0x010011 0x0 0x0>;

};



&blsp1_uart1 {

	status = "ok";

};

arch/arm/boot/dts/qcom/msm8917-pinctrl.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -128,6 +128,38 @@ 


		};



		blsp1_uart1 {

			blsp1_uart1_active: blsp1_uart1_active {

				mux {

					pins = "gpio0", "gpio1",

						"gpio2", "gpio3";

					function = "blsp_uart1";

				};



				config {

					pins = "gpio0", "gpio1",

						"gpio2", "gpio3";

					drive-strength = <2>;

					bias-disable;

				};

			};



			blsp1_uart1_sleep: blsp1_uart1_sleep {

				mux {

					pins = "gpio0", "gpio1",

						"gpio2", "gpio3";

					function = "gpio";

				};



				config {

					pins = "gpio0", "gpio1",

						"gpio2", "gpio3";

					drive-strength = <2>;

					bias-disable;

				};

			};

		};



		wcnss_pmux_5wire {

			/* Active configuration of bus pins */

			wcnss_default: wcnss_default {

arch/arm/boot/dts/qcom/msm8917.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -454,6 +454,43 @@ 
		clock-names = "core_clk", "iface_clk";

	};



	blsp1_uart1: uart@78af000 { /* BLSP1 UART1 */

		compatible = "qcom,msm-hsuart-v14";

		#address-cells = <0>;

		#interrupt-cells = <1>;

		reg = <0x78af000 0x200>,

			<0x7884000 0x1f000>;

		reg-names = "core_mem", "bam_mem";

		interrupt-parent = <&blsp1_uart1>;

		interrupts = <0 1 2>;

		interrupt-names = "core_irq", "bam_irq", "wakeup_irq";

		interrupt-map = <0 &intc 0 107 0

				1 &intc 0 238 0

				2 &tlmm 1 0>;

		interrupt-map-mask = <0xffffffff>;



		qcom,inject-rx-on-wakeup;

		qcom,rx-char-to-inject = <0xFD>;



		qcom,bam-tx-ep-pipe-index = <0>;

		qcom,bam-rx-ep-pipe-index = <1>;

		qcom,master-id = <86>;

		clock-names = "core_clk", "iface_clk";

		clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,

			<&clock_gcc clk_gcc_blsp1_ahb_clk>;

		pinctrl-names = "sleep", "default";

		pinctrl-0 = <&blsp1_uart1_sleep>;

		pinctrl-1 = <&blsp1_uart1_active>;



		qcom,msm-bus,name = "blsp1_uart1";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<86 512 0 0>,

				<86 512 500 800>;

		status = "disabled";

	};



	dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */

		#dma-cells = <4>;

		compatible = "qcom,sps-dma";