Commit ad183c04 authored Apr 17, 2015 by David Collins Committed by Gerrit - the friendly Code Review server Jun 03, 2015

ARM: dts: msm: enable VDD_APCC CPR clock throttling for msm8996



Enable VDD_APCC CPR clock throttling so that the performance
cluster clock rate is reduced whenever the performance cluster
L2 SPM exits from a low power mode.  This ensures that the
VDD_APCC voltage is stepped back up to a level that is sufficient
for the commanded performance cluster frequency.  Once the
VDD_APCC voltage stabilizes, the performance cluster clock is
switched to the commanded frequency.

Change-Id: Id7ac729e30403a1d2478ac2cfeebf95d40ca62ca
Signed-off-by: David Collins <collinsd@codeaurora.org>

parent fd2bc04d

arch/arm/boot/dts/qcom/msm8996-regulator.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -576,6 +576,7 @@

		qcom,cpr-enable;
		qcom,cpr-hw-closed-loop;
		qcom,cpr-clock-throttling = <0x20>;

		apc0_vreg: regulator@0 {
		qcom,cpr-thread-id = <0>;