ARM: dts: msm: enable VDD_APCC CPR clock throttling for msm8996

Enable VDD_APCC CPR clock throttling so that the performance
cluster clock rate is reduced whenever the performance cluster
L2 SPM exits from a low power mode.  This ensures that the
VDD_APCC voltage is stepped back up to a level that is sufficient
for the commanded performance cluster frequency.  Once the
VDD_APCC voltage stabilizes, the performance cluster clock is
switched to the commanded frequency.

Change-Id: Id7ac729e30403a1d2478ac2cfeebf95d40ca62ca
Signed-off-by: David Collins <collinsd@codeaurora.org>