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Commit fd2bc04d authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

clk: msm: clock-alpha-pll: Wait for the FSM to turn off the PLL 



It is necessary to check that a PLL is completely disabled
before invoking code that would modify PLL configuration.
For FSM controlled PLLs, check the PLL active flag before
exiting the function since we may be in a set_rate op on
the PLL.

This is really not necessary for other FSM controlled PLLs
that have a fixed rate.

Change-Id: I6b0e4e6a0ccfa7949a1996fb8911e1f7044d725a
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent f388a43a

drivers/clk/msm/clock-alpha-pll.c

+3 −3
Original line number Diff line number Diff line
@@ -178,6 +178,7 @@ static int alpha_pll_enable(struct clk *c) 
#define PLL_OFFLINE_REQ_BIT BIT(7)

#define PLL_FSM_ENA_BIT BIT(20)

#define PLL_OFFLINE_ACK_BIT BIT(28)

#define PLL_ACTIVE_FLAG BIT(30)



static int alpha_pll_enable_hwfsm(struct clk *c)

{
@@ -215,9 +216,8 @@ static void alpha_pll_disable_hwfsm(struct clk *c) 
	mode &= ~PLL_FSM_ENA_BIT;

	writel_relaxed(mode, MODE_REG(pll));



	/* Wait for FSM to disable the PLL */

	mb();

	udelay(5);

	while (readl_relaxed(MODE_REG(pll)) & PLL_ACTIVE_FLAG)

		;

}



static void __alpha_pll_vote_disable(struct alpha_pll_clk *pll)