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Commit aa4a6250 authored by John W. Linville's avatar John W. Linville
Browse files
parents 2df3b0b7 a82dda6c
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+3 −1
Original line number Diff line number Diff line
@@ -2039,7 +2039,7 @@ static void iwl_free_skb(struct iwl_op_mode *op_mode, struct sk_buff *skb)
	ieee80211_free_txskb(priv->hw, skb);
}

static void iwl_set_hw_rfkill_state(struct iwl_op_mode *op_mode, bool state)
static bool iwl_set_hw_rfkill_state(struct iwl_op_mode *op_mode, bool state)
{
	struct iwl_priv *priv = IWL_OP_MODE_GET_DVM(op_mode);

@@ -2049,6 +2049,8 @@ static void iwl_set_hw_rfkill_state(struct iwl_op_mode *op_mode, bool state)
		clear_bit(STATUS_RF_KILL_HW, &priv->status);

	wiphy_rfkill_set_hw_state(priv->hw->wiphy, state);

	return false;
}

static const struct iwl_op_mode_ops iwl_dvm_ops = {
+4 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ const struct iwl_cfg iwl7260_2ac_cfg = {
	.nvm_ver = IWL7260_NVM_VERSION,
	.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
	.host_interrupt_operation_mode = true,
	.lp_xtal_workaround = true,
};

const struct iwl_cfg iwl7260_2ac_cfg_high_temp = {
@@ -145,6 +146,7 @@ const struct iwl_cfg iwl7260_2ac_cfg_high_temp = {
	.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
	.high_temp = true,
	.host_interrupt_operation_mode = true,
	.lp_xtal_workaround = true,
};

const struct iwl_cfg iwl7260_2n_cfg = {
@@ -155,6 +157,7 @@ const struct iwl_cfg iwl7260_2n_cfg = {
	.nvm_ver = IWL7260_NVM_VERSION,
	.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
	.host_interrupt_operation_mode = true,
	.lp_xtal_workaround = true,
};

const struct iwl_cfg iwl7260_n_cfg = {
@@ -165,6 +168,7 @@ const struct iwl_cfg iwl7260_n_cfg = {
	.nvm_ver = IWL7260_NVM_VERSION,
	.nvm_calib_ver = IWL7260_TX_POWER_VERSION,
	.host_interrupt_operation_mode = true,
	.lp_xtal_workaround = true,
};

const struct iwl_cfg iwl3160_2ac_cfg = {
+1 −0
Original line number Diff line number Diff line
@@ -262,6 +262,7 @@ struct iwl_cfg {
	bool high_temp;
	bool d0i3;
	u8   nvm_hw_section_num;
	bool lp_xtal_workaround;
	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
};

+38 −0
Original line number Diff line number Diff line
@@ -138,6 +138,13 @@
/* Analog phase-lock-loop configuration  */
#define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)

/*
 * CSR HW resources monitor registers
 */
#define CSR_MONITOR_CFG_REG		(CSR_BASE+0x214)
#define CSR_MONITOR_STATUS_REG		(CSR_BASE+0x228)
#define CSR_MONITOR_XTAL_RESOURCES	(0x00000010)

/*
 * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
 * "step" determines CCK backoff for txpower calculation.  Used for 4965 only.
@@ -173,6 +180,7 @@
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY	(0x00400000) /* PCI_OWN_SEM */
#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
#define CSR_HW_IF_CONFIG_REG_PREPARE		  (0x08000000) /* WAKE_ME */
#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE	  (0x40000000) /* PERSISTENCE */

#define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
#define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/
@@ -240,6 +248,7 @@
 *         001 -- MAC power-down
 *         010 -- PHY (radio) power-down
 *         011 -- Error
 *    10:  XTAL ON request
 *   9-6:  SYS_CONFIG
 *         Indicates current system configuration, reflecting pins on chip
 *         as forced high/low by device circuit board.
@@ -271,6 +280,7 @@
#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE              (0x00000004)
#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ         (0x00000008)
#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON		     (0x00000400)

#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN           (0x00000001)

@@ -395,6 +405,34 @@
#define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
#define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)

/*
 * SHR target access (Shared block memory space)
 *
 * Shared internal registers can be accessed directly from PCI bus through SHR
 * arbiter without need for the MAC HW to be powered up. This is possible due to
 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
 *
 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
 * need not be powered up so no "grab inc access" is required.
 */

/*
 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
 * first, write to the control register:
 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
 *
 * To write the register, first, write to the data register
 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
 */
#define HEEP_CTRL_WRD_PCIEX_CTRL_REG	(CSR_BASE+0x0ec)
#define HEEP_CTRL_WRD_PCIEX_DATA_REG	(CSR_BASE+0x0f4)

/*
 * HBUS (Host-side Bus)
 *
+16 −0
Original line number Diff line number Diff line
@@ -125,6 +125,22 @@ enum iwl_ucode_tlv_flag {
	IWL_UCODE_TLV_FLAGS_GO_UAPSD		= BIT(30),
};

/**
 * enum iwl_ucode_tlv_api - ucode api
 * @IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID: wowlan config includes tid field.
 */
enum iwl_ucode_tlv_api {
	IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID	= BIT(0),
};

/**
 * enum iwl_ucode_tlv_capa - ucode capabilities
 * @IWL_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
 */
enum iwl_ucode_tlv_capa {
	IWL_UCODE_TLV_CAPA_D0I3_SUPPORT		= BIT(0),
};

/* The default calibrate table size if not specified by firmware file */
#define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE	18
#define IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE		19
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