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Commit a7df42cf authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "iommu: Introduce DOMAIN_ATTR_S1_BYPASS"

parents d4fe4a7d bb637579

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+0 −12
Original line number Diff line number Diff line
@@ -86,18 +86,6 @@ conditions. 
                  Thulium v1.  You *must* also set qcom,tz-device-id for

                  this to work.



- qcom,no-mmu-enable : When attaching to this SMMU, program everything as

                  usual (stream matching table, etc) but leave the SCTLR.M

                  bit disabled, so that the SMMU doesn't actually perform

                  translations.  This is needed in cases where the stream

                  matching table needs to be set up without turning on SMMU

                  translations (for example, when nested translations are

                  used with a hypervisor controlling stage-2).  This mode of

                  operation is described in the ARM SMMU spec as "stage 1

                  and stage 2 contexts are valid, but the SMMU is not

                  enabled for stage 1 translation" (Section 2.1: "Overview

                  of SMMU operation").



- qcom,no-smr-check : Usually when an SMMU probes we do a sanity check on

                  the SMR registers to make sure they can fully support all

                  of the mask bits.  This check can cause problems for use

drivers/iommu/arm-smmu.c

+1 −5
Original line number Diff line number Diff line
@@ -359,7 +359,6 @@ struct arm_smmu_device { 
#define ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG (1 << 5)

#define ARM_SMMU_OPT_FATAL_ASF		(1 << 6)

#define ARM_SMMU_OPT_ERRATA_TZ_ATOS	(1 << 7)

#define ARM_SMMU_OPT_NO_M		(1 << 8)

#define ARM_SMMU_OPT_NO_SMR_CHECK	(1 << 9)

#define ARM_SMMU_OPT_DYNAMIC		(1 << 10)

#define ARM_SMMU_OPT_HALT		(1 << 11)
@@ -480,7 +479,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG, "qcom,errata-ctx-fault-hang" },

	{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },

	{ ARM_SMMU_OPT_ERRATA_TZ_ATOS, "qcom,errata-tz-atos" },

	{ ARM_SMMU_OPT_NO_M, "qcom,no-mmu-enable" },

	{ ARM_SMMU_OPT_NO_SMR_CHECK, "qcom,no-smr-check" },

	{ ARM_SMMU_OPT_DYNAMIC, "qcom,dynamic" },

	{ ARM_SMMU_OPT_HALT, "qcom,enable-smmu-halt"},
@@ -1470,9 +1468,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, 
	}



	/* SCTLR */

	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP;

	if (!(smmu->options & ARM_SMMU_OPT_NO_M))

		reg |= SCTLR_M;

	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;

	if (stage1)

		reg |= SCTLR_S1_ASIDPNE;

#ifdef __BIG_ENDIAN

include/linux/iommu.h

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ enum iommu_attr { 
	DOMAIN_ATTR_PROCID,

	DOMAIN_ATTR_DYNAMIC,

	DOMAIN_ATTR_NON_FATAL_FAULTS,

	DOMAIN_ATTR_S1_BYPASS,

	DOMAIN_ATTR_MAX,

};