Loading arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +0 −7 Original line number Diff line number Diff line Loading @@ -13,13 +13,6 @@ &soc { /* GCC GDSCs */ gdsc_mmss: qcom,gdsc@109004 { compatible = "qcom,gdsc"; regulator-name = "gdsc_mmss"; reg = <0x109004 0x4>; status = "disabled"; }; gdsc_usb30: qcom,gdsc@10f004 { compatible = "qcom,gdsc"; regulator-name = "gdsc_usb30"; Loading arch/arm/boot/dts/qcom/msmcobalt.dtsi +0 −4 Original line number Diff line number Diff line Loading @@ -1881,10 +1881,6 @@ }; }; &gdsc_mmss { status = "ok"; }; &gdsc_usb30 { clock-names = "core_clk"; clocks = <&clock_gcc clk_gcc_usb30_master_clk>; Loading Loading
arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +0 −7 Original line number Diff line number Diff line Loading @@ -13,13 +13,6 @@ &soc { /* GCC GDSCs */ gdsc_mmss: qcom,gdsc@109004 { compatible = "qcom,gdsc"; regulator-name = "gdsc_mmss"; reg = <0x109004 0x4>; status = "disabled"; }; gdsc_usb30: qcom,gdsc@10f004 { compatible = "qcom,gdsc"; regulator-name = "gdsc_usb30"; Loading
arch/arm/boot/dts/qcom/msmcobalt.dtsi +0 −4 Original line number Diff line number Diff line Loading @@ -1881,10 +1881,6 @@ }; }; &gdsc_mmss { status = "ok"; }; &gdsc_usb30 { clock-names = "core_clk"; clocks = <&clock_gcc clk_gcc_usb30_master_clk>; Loading