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Commit a0289f91 authored by J Keerthy's avatar J Keerthy Committed by Mike Turquette
Browse files

ARM: dts: DRA7: Add PCIe related clock nodes 



This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.

Signed-off-by: default avatarJ Keerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Tested-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent c3be7acd

arch/arm/boot/dts/dra7xx-clocks.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -1165,6 +1165,31 @@ 
		reg = <0x021c>, <0x0220>;

	};



	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {

		compatible = "ti,divider-clock";

		clocks = <&apll_pcie_ck>;

		#clock-cells = <0>;

		reg = <0x021c>;

		ti,bit-shift = <8>;

		ti,max-div = <2>;

	};



	optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {

		compatible = "ti,gate-clock";

		clocks = <&apll_pcie_ck>;

		#clock-cells = <0>;

		reg = <0x13b0>;

		ti,bit-shift = <9>;

	};



	optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {

		compatible = "ti,gate-clock";

		clocks = <&optfclk_pciephy_div>;

		#clock-cells = <0>;

		reg = <0x13b0>;

		ti,bit-shift = <10>;

	};



	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";