Loading drivers/hwtracing/coresight/coresight-etm3x.c +51 −49 Original line number Diff line number Diff line Loading @@ -313,14 +313,6 @@ static void etm_enable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); } static int etm_trace_id_simple(struct etm_drvdata *drvdata) { if (!drvdata->enable) return drvdata->traceid; return (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); } static int etm_trace_id(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); Loading Loading @@ -1506,45 +1498,6 @@ static ssize_t timestamp_event_store(struct device *dev, } static DEVICE_ATTR_RW(timestamp_event); static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { int ret; unsigned long flags; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); ret = sprintf(buf, "ETMCCR: 0x%08x\n" "ETMCCER: 0x%08x\n" "ETMSCR: 0x%08x\n" "ETMIDR: 0x%08x\n" "ETMCR: 0x%08x\n" "ETMTRACEIDR: 0x%08x\n" "Enable event: 0x%08x\n" "Enable start/stop: 0x%08x\n" "Enable control: CR1 0x%08x CR2 0x%08x\n" "CPU affinity: %d\n", drvdata->etmccr, drvdata->etmccer, etm_readl(drvdata, ETMSCR), etm_readl(drvdata, ETMIDR), etm_readl(drvdata, ETMCR), etm_trace_id_simple(drvdata), etm_readl(drvdata, ETMTEEVR), etm_readl(drvdata, ETMTSSCR), etm_readl(drvdata, ETMTECR1), etm_readl(drvdata, ETMTECR2), drvdata->cpu); CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(drvdata->dev); return ret; } static DEVICE_ATTR_RO(status); static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { Loading Loading @@ -1631,12 +1584,61 @@ static struct attribute *coresight_etm_attrs[] = { &dev_attr_ctxid_mask.attr, &dev_attr_sync_freq.attr, &dev_attr_timestamp_event.attr, &dev_attr_status.attr, &dev_attr_traceid.attr, &dev_attr_cpu.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_etm); #define coresight_simple_func(name, offset) \ static ssize_t name##_show(struct device *_dev, \ struct device_attribute *attr, char *buf) \ { \ struct etm_drvdata *drvdata = dev_get_drvdata(_dev->parent); \ return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ readl_relaxed(drvdata->base + offset)); \ } \ DEVICE_ATTR_RO(name) coresight_simple_func(etmccr, ETMCCR); coresight_simple_func(etmccer, ETMCCER); coresight_simple_func(etmscr, ETMSCR); coresight_simple_func(etmidr, ETMIDR); coresight_simple_func(etmcr, ETMCR); coresight_simple_func(etmtraceidr, ETMTRACEIDR); coresight_simple_func(etmteevr, ETMTEEVR); coresight_simple_func(etmtssvr, ETMTSSCR); coresight_simple_func(etmtecr1, ETMTECR1); coresight_simple_func(etmtecr2, ETMTECR2); static struct attribute *coresight_etm_mgmt_attrs[] = { &dev_attr_etmccr.attr, &dev_attr_etmccer.attr, &dev_attr_etmscr.attr, &dev_attr_etmidr.attr, &dev_attr_etmcr.attr, &dev_attr_etmtraceidr.attr, &dev_attr_etmteevr.attr, &dev_attr_etmtssvr.attr, &dev_attr_etmtecr1.attr, &dev_attr_etmtecr2.attr, NULL, }; static const struct attribute_group coresight_etm_group = { .attrs = coresight_etm_attrs, }; static const struct attribute_group coresight_etm_mgmt_group = { .attrs = coresight_etm_mgmt_attrs, .name = "mgmt", }; static const struct attribute_group *coresight_etm_groups[] = { &coresight_etm_group, &coresight_etm_mgmt_group, NULL, }; static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) Loading Loading
drivers/hwtracing/coresight/coresight-etm3x.c +51 −49 Original line number Diff line number Diff line Loading @@ -313,14 +313,6 @@ static void etm_enable_hw(void *info) dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu); } static int etm_trace_id_simple(struct etm_drvdata *drvdata) { if (!drvdata->enable) return drvdata->traceid; return (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); } static int etm_trace_id(struct coresight_device *csdev) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); Loading Loading @@ -1506,45 +1498,6 @@ static ssize_t timestamp_event_store(struct device *dev, } static DEVICE_ATTR_RW(timestamp_event); static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { int ret; unsigned long flags; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); ret = sprintf(buf, "ETMCCR: 0x%08x\n" "ETMCCER: 0x%08x\n" "ETMSCR: 0x%08x\n" "ETMIDR: 0x%08x\n" "ETMCR: 0x%08x\n" "ETMTRACEIDR: 0x%08x\n" "Enable event: 0x%08x\n" "Enable start/stop: 0x%08x\n" "Enable control: CR1 0x%08x CR2 0x%08x\n" "CPU affinity: %d\n", drvdata->etmccr, drvdata->etmccer, etm_readl(drvdata, ETMSCR), etm_readl(drvdata, ETMIDR), etm_readl(drvdata, ETMCR), etm_trace_id_simple(drvdata), etm_readl(drvdata, ETMTEEVR), etm_readl(drvdata, ETMTSSCR), etm_readl(drvdata, ETMTECR1), etm_readl(drvdata, ETMTECR2), drvdata->cpu); CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(drvdata->dev); return ret; } static DEVICE_ATTR_RO(status); static ssize_t cpu_show(struct device *dev, struct device_attribute *attr, char *buf) { Loading Loading @@ -1631,12 +1584,61 @@ static struct attribute *coresight_etm_attrs[] = { &dev_attr_ctxid_mask.attr, &dev_attr_sync_freq.attr, &dev_attr_timestamp_event.attr, &dev_attr_status.attr, &dev_attr_traceid.attr, &dev_attr_cpu.attr, NULL, }; ATTRIBUTE_GROUPS(coresight_etm); #define coresight_simple_func(name, offset) \ static ssize_t name##_show(struct device *_dev, \ struct device_attribute *attr, char *buf) \ { \ struct etm_drvdata *drvdata = dev_get_drvdata(_dev->parent); \ return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ readl_relaxed(drvdata->base + offset)); \ } \ DEVICE_ATTR_RO(name) coresight_simple_func(etmccr, ETMCCR); coresight_simple_func(etmccer, ETMCCER); coresight_simple_func(etmscr, ETMSCR); coresight_simple_func(etmidr, ETMIDR); coresight_simple_func(etmcr, ETMCR); coresight_simple_func(etmtraceidr, ETMTRACEIDR); coresight_simple_func(etmteevr, ETMTEEVR); coresight_simple_func(etmtssvr, ETMTSSCR); coresight_simple_func(etmtecr1, ETMTECR1); coresight_simple_func(etmtecr2, ETMTECR2); static struct attribute *coresight_etm_mgmt_attrs[] = { &dev_attr_etmccr.attr, &dev_attr_etmccer.attr, &dev_attr_etmscr.attr, &dev_attr_etmidr.attr, &dev_attr_etmcr.attr, &dev_attr_etmtraceidr.attr, &dev_attr_etmteevr.attr, &dev_attr_etmtssvr.attr, &dev_attr_etmtecr1.attr, &dev_attr_etmtecr2.attr, NULL, }; static const struct attribute_group coresight_etm_group = { .attrs = coresight_etm_attrs, }; static const struct attribute_group coresight_etm_mgmt_group = { .attrs = coresight_etm_mgmt_attrs, .name = "mgmt", }; static const struct attribute_group *coresight_etm_groups[] = { &coresight_etm_group, &coresight_etm_mgmt_group, NULL, }; static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) Loading