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Commit 9d971b37 authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Keith Packard
Browse files

drm/i915: Rename PIPE_CONTROL bit defines to be less terse. 



"STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are
several different kinds of stalls.  Also, "INSTRUCTION_CACHE_INVALIDATE"
is a lot easier to understand at a glance than the terse "IS_FLUSH."

Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
[danvet: use INVALIDATE for ro cache flags for more consistency]
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent fcbc34e4

drivers/gpu/drm/i915/i915_reg.h

+8 −8
Original line number Original line Diff line number Diff line
@@ -245,13 +245,13 @@ 
#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_QW_WRITE				(1<<14)

#define   PIPE_CONTROL_QW_WRITE				(1<<14)

#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)

#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)

#define   PIPE_CONTROL_WC_FLUSH	(1<<12)

#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)

#define   PIPE_CONTROL_IS_FLUSH	(1<<11) /* MBZ on Ironlake */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on Ironlake */

#define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */

#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_ISP_DIS	(1<<9)

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_NOTIFY				(1<<8)

#define   PIPE_CONTROL_NOTIFY				(1<<8)

#define   PIPE_CONTROL_STALL_AT_SCOREBOARD		(1<<1)

#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */

#define   PIPE_CONTROL_STALL_EN	(1<<1) /* in addr word, Ironlake+ only */









/*

/*

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -468,7 +468,8 @@ pc_render_add_request(struct intel_ring_buffer *ring, 
		return ret;

		return ret;





	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);

			PIPE_CONTROL_WRITE_FLUSH |

			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, seqno);

	intel_ring_emit(ring, seqno);

	intel_ring_emit(ring, 0);

	intel_ring_emit(ring, 0);
@@ -484,7 +485,8 @@ pc_render_add_request(struct intel_ring_buffer *ring, 
	scratch_addr += 128;

	scratch_addr += 128;

	PIPE_CONTROL_FLUSH(ring, scratch_addr);

	PIPE_CONTROL_FLUSH(ring, scratch_addr);

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |

			PIPE_CONTROL_WRITE_FLUSH |

			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |

			PIPE_CONTROL_NOTIFY);

			PIPE_CONTROL_NOTIFY);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, seqno);

	intel_ring_emit(ring, seqno);