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Commit fcbc34e4 authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Keith Packard
Browse files

drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define. 



Not all PIPE_CONTROLs have a length of 2, so remove it from the #define
and make each invocation specify the desired length.

Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
[danvet: implement style suggestion from Ben Widawsdy]
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent b73fe58c

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ 
#define   ASYNC_FLIP                (1<<22)

#define   DISPLAY_PLANE_A           (0<<20)

#define   DISPLAY_PLANE_B           (1<<20)

#define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)

#define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))

#define   PIPE_CONTROL_QW_WRITE	(1<<14)

#define   PIPE_CONTROL_DEPTH_STALL (1<<13)

#define   PIPE_CONTROL_WC_FLUSH	(1<<12)

drivers/gpu/drm/i915/intel_ringbuffer.c

+4 −4
Original line number Diff line number Diff line
@@ -438,8 +438,8 @@ gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, 


#define PIPE_CONTROL_FLUSH(ring__, addr__)					\

do {									\

	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |		\

		 PIPE_CONTROL_DEPTH_STALL | 2);				\

	intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |		\

		 PIPE_CONTROL_DEPTH_STALL);				\

	intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);			\

	intel_ring_emit(ring__, 0);							\

	intel_ring_emit(ring__, 0);							\
@@ -467,7 +467,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, 
	if (ret)

		return ret;



	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);

	intel_ring_emit(ring, seqno);
@@ -483,7 +483,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, 
	PIPE_CONTROL_FLUSH(ring, scratch_addr);

	scratch_addr += 128;

	PIPE_CONTROL_FLUSH(ring, scratch_addr);

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |

	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |

			PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |

			PIPE_CONTROL_NOTIFY);

	intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);