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Commit 996f21e4 authored by Taniya Das's avatar Taniya Das
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clk: msm: Add support for fractional offset for Alpha PLL



There could be Fabia PLLs whose fractional value register offset would not
align to the current offset, leading to computing and updating wrong
fractional offset. Add support to take the offset as an input and
use the user defined offset to calculate the fractional value.

Change-Id: Icbdb8d5188b6f51269236d379ffa6826539e2a41
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent be44f30e
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+10 −2
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@
#define FABIA_L_REG(pll)		(*pll->base + pll->offset + 0x4)
#define FABIA_FRAC_REG(pll)		(*pll->base + pll->offset + 0x38)
#define FABIA_PLL_OPMODE(pll)		(*pll->base + pll->offset + 0x2c)
#define FABIA_FRAC_OFF(pll)		(*pll->base + pll->fabia_frac_offset)

#define FABIA_PLL_STANDBY	0x0
#define FABIA_PLL_RUN		0x1
@@ -977,6 +978,9 @@ static int fabia_alpha_pll_set_rate(struct clk *c, unsigned long rate)
	spin_lock_irqsave(&c->lock, flags);
	/* Set the new L value */
	writel_relaxed(l_val, FABIA_L_REG(pll));
	if (pll->fabia_frac_offset)
		writel_relaxed(a_val, FABIA_FRAC_OFF(pll));
	else
		writel_relaxed(a_val, FABIA_FRAC_REG(pll));

	alpha_pll_dynamic_update(pll);
@@ -1055,6 +1059,10 @@ static enum handoff fabia_alpha_pll_handoff(struct clk *c)
	}

	l_val = readl_relaxed(FABIA_L_REG(pll));

	if (pll->fabia_frac_offset)
		a_val = readl_relaxed(FABIA_FRAC_OFF(pll));
	else
		a_val = readl_relaxed(FABIA_FRAC_REG(pll));

	c->rate = compute_rate(pll, l_val, a_val);
+2 −1
Original line number Diff line number Diff line
/*
 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
 * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -48,6 +48,7 @@ struct alpha_pll_clk {
	struct alpha_pll_masks *masks;
	void *const __iomem *base;
	u32 offset;
	u32 fabia_frac_offset;

	/* if fsm_en_mask is set, config PLL to FSM mode */
	u32 fsm_reg_offset;