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Commit 976face4 authored by Rahul Sharma's avatar Rahul Sharma Committed by Tomasz Figa
Browse files

clk/samsung: add support for multiple clock providers 



Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.

This layer is modified accordingly to enable the support
for multiple clock providers.

Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c24xx are also modified as per changed helper functions.

Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
[t.figa: Modified s3c2410 clock driver as well]
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 2916f9a2

drivers/clk/samsung/clk-exynos4.c

+25 −22
Original line number Diff line number Diff line
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void) 
	return xom;

}



static void __init exynos4_clk_register_finpll(void)

static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)

{

	struct samsung_fixed_rate_clock fclk;

	struct clk *clk;
@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void) 
	fclk.parent_name = NULL;

	fclk.flags = CLK_IS_ROOT;

	fclk.fixed_rate = finpll_f;

	samsung_clk_register_fixed_rate(&fclk, 1);

	samsung_clk_register_fixed_rate(ctx, &fclk, 1);



}
@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 
static void __init exynos4_clk_init(struct device_node *np,

				    enum exynos4_soc soc)

{

	struct samsung_clk_provider *ctx;

	exynos4_soc = soc;



	reg_base = of_iomap(np, 0);

	if (!reg_base)

		panic("%s: failed to map registers\n", __func__);



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);



	samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,

	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),

			ext_clk_match);



	exynos4_clk_register_finpll();

	exynos4_clk_register_finpll(ctx);



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_register_mux(exynos4210_mux_early,

		samsung_clk_register_mux(ctx, exynos4210_mux_early,

					ARRAY_SIZE(exynos4210_mux_early));



		if (_get_rate("fin_pll") == 24000000) {
@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
			exynos4210_plls[vpll].rate_table =

							exynos4210_vpll_rates;



		samsung_clk_register_pll(exynos4210_plls,

		samsung_clk_register_pll(ctx, exynos4210_plls,

					ARRAY_SIZE(exynos4210_plls), reg_base);

	} else {

		if (_get_rate("fin_pll") == 24000000) {
@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node *np, 
							exynos4x12_vpll_rates;

		}



		samsung_clk_register_pll(exynos4x12_plls,

		samsung_clk_register_pll(ctx, exynos4x12_plls,

					ARRAY_SIZE(exynos4x12_plls), reg_base);

	}



	samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

			ARRAY_SIZE(exynos4_fixed_rate_clks));

	samsung_clk_register_mux(exynos4_mux_clks,

	samsung_clk_register_mux(ctx, exynos4_mux_clks,

			ARRAY_SIZE(exynos4_mux_clks));

	samsung_clk_register_div(exynos4_div_clks,

	samsung_clk_register_div(ctx, exynos4_div_clks,

			ARRAY_SIZE(exynos4_div_clks));

	samsung_clk_register_gate(exynos4_gate_clks,

	samsung_clk_register_gate(ctx, exynos4_gate_clks,

			ARRAY_SIZE(exynos4_gate_clks));



	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,

		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,

			ARRAY_SIZE(exynos4210_fixed_rate_clks));

		samsung_clk_register_mux(exynos4210_mux_clks,

		samsung_clk_register_mux(ctx, exynos4210_mux_clks,

			ARRAY_SIZE(exynos4210_mux_clks));

		samsung_clk_register_div(exynos4210_div_clks,

		samsung_clk_register_div(ctx, exynos4210_div_clks,

			ARRAY_SIZE(exynos4210_div_clks));

		samsung_clk_register_gate(exynos4210_gate_clks,

		samsung_clk_register_gate(ctx, exynos4210_gate_clks,

			ARRAY_SIZE(exynos4210_gate_clks));

		samsung_clk_register_alias(exynos4210_aliases,

		samsung_clk_register_alias(ctx, exynos4210_aliases,

			ARRAY_SIZE(exynos4210_aliases));

	} else {

		samsung_clk_register_mux(exynos4x12_mux_clks,

		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,

			ARRAY_SIZE(exynos4x12_mux_clks));

		samsung_clk_register_div(exynos4x12_div_clks,

		samsung_clk_register_div(ctx, exynos4x12_div_clks,

			ARRAY_SIZE(exynos4x12_div_clks));

		samsung_clk_register_gate(exynos4x12_gate_clks,

		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,

			ARRAY_SIZE(exynos4x12_gate_clks));

		samsung_clk_register_alias(exynos4x12_aliases,

		samsung_clk_register_alias(ctx, exynos4x12_aliases,

			ARRAY_SIZE(exynos4x12_aliases));

	}



	samsung_clk_register_alias(exynos4_aliases,

	samsung_clk_register_alias(ctx, exynos4_aliases,

			ARRAY_SIZE(exynos4_aliases));



	exynos4_clk_sleep_init();

drivers/clk/samsung/clk-exynos5250.c

+15 −10
Original line number Diff line number Diff line
@@ -686,6 +686,8 @@ static struct of_device_id ext_clk_match[] __initdata = { 
/* register exynox5250 clocks */

static void __init exynos5250_clk_init(struct device_node *np)

{

	struct samsung_clk_provider *ctx;



	if (np) {

		reg_base = of_iomap(np, 0);

		if (!reg_base)
@@ -694,11 +696,13 @@ static void __init exynos5250_clk_init(struct device_node *np) 
		panic("%s: unable to determine soc\n", __func__);

	}



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);

	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),

			ext_clk_match);

	samsung_clk_register_mux(exynos5250_pll_pmux_clks,

	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,

				ARRAY_SIZE(exynos5250_pll_pmux_clks));



	if (_get_rate("fin_pll") == 24 * MHZ) {
@@ -709,17 +713,18 @@ static void __init exynos5250_clk_init(struct device_node *np) 
	if (_get_rate("mout_vpllsrc") == 24 * MHZ)

		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;



	samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),

	samsung_clk_register_pll(ctx, exynos5250_plls,

			ARRAY_SIZE(exynos5250_plls),

			reg_base);

	samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_clks));

	samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,

	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,

			ARRAY_SIZE(exynos5250_fixed_factor_clks));

	samsung_clk_register_mux(exynos5250_mux_clks,

	samsung_clk_register_mux(ctx, exynos5250_mux_clks,

			ARRAY_SIZE(exynos5250_mux_clks));

	samsung_clk_register_div(exynos5250_div_clks,

	samsung_clk_register_div(ctx, exynos5250_div_clks,

			ARRAY_SIZE(exynos5250_div_clks));

	samsung_clk_register_gate(exynos5250_gate_clks,

	samsung_clk_register_gate(ctx, exynos5250_gate_clks,

			ARRAY_SIZE(exynos5250_gate_clks));



	exynos5250_clk_sleep_init();

drivers/clk/samsung/clk-exynos5420.c

+15 −9
Original line number Diff line number Diff line
@@ -778,6 +778,8 @@ static struct of_device_id ext_clk_match[] __initdata = { 
/* register exynos5420 clocks */

static void __init exynos5420_clk_init(struct device_node *np)

{

	struct samsung_clk_provider *ctx;



	if (np) {

		reg_base = of_iomap(np, 0);

		if (!reg_base)
@@ -786,21 +788,25 @@ static void __init exynos5420_clk_init(struct device_node *np) 
		panic("%s: unable to determine soc\n", __func__);

	}



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);



	samsung_clk_of_register_fixed_ext(ctx, exynos5420_fixed_rate_ext_clks,

			ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),

			ext_clk_match);

	samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),

	samsung_clk_register_pll(ctx, exynos5420_plls,

			ARRAY_SIZE(exynos5420_plls),

			reg_base);

	samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos5420_fixed_rate_clks,

			ARRAY_SIZE(exynos5420_fixed_rate_clks));

	samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,

	samsung_clk_register_fixed_factor(ctx, exynos5420_fixed_factor_clks,

			ARRAY_SIZE(exynos5420_fixed_factor_clks));

	samsung_clk_register_mux(exynos5420_mux_clks,

	samsung_clk_register_mux(ctx, exynos5420_mux_clks,

			ARRAY_SIZE(exynos5420_mux_clks));

	samsung_clk_register_div(exynos5420_div_clks,

	samsung_clk_register_div(ctx, exynos5420_div_clks,

			ARRAY_SIZE(exynos5420_div_clks));

	samsung_clk_register_gate(exynos5420_gate_clks,

	samsung_clk_register_gate(ctx, exynos5420_gate_clks,

			ARRAY_SIZE(exynos5420_gate_clks));



	exynos5420_clk_sleep_init();

drivers/clk/samsung/clk-exynos5440.c

+11 −7
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ static struct of_device_id ext_clk_match[] __initdata = { 
static void __init exynos5440_clk_init(struct device_node *np)

{

	void __iomem *reg_base;

	struct samsung_clk_provider *ctx;



	reg_base = of_iomap(np, 0);

	if (!reg_base) {
@@ -101,22 +102,25 @@ static void __init exynos5440_clk_init(struct device_node *np) 
		return;

	}



	samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	if (!ctx)

		panic("%s: unable to allocate context.\n", __func__);



	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,

		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);



	samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);

	samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);



	samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,

	samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,

			ARRAY_SIZE(exynos5440_fixed_rate_clks));

	samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,

	samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,

			ARRAY_SIZE(exynos5440_fixed_factor_clks));

	samsung_clk_register_mux(exynos5440_mux_clks,

	samsung_clk_register_mux(ctx, exynos5440_mux_clks,

			ARRAY_SIZE(exynos5440_mux_clks));

	samsung_clk_register_div(exynos5440_div_clks,

	samsung_clk_register_div(ctx, exynos5440_div_clks,

			ARRAY_SIZE(exynos5440_div_clks));

	samsung_clk_register_gate(exynos5440_gate_clks,

	samsung_clk_register_gate(ctx, exynos5440_gate_clks,

			ARRAY_SIZE(exynos5440_gate_clks));



	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));

drivers/clk/samsung/clk-pll.c

+8 −6
Original line number Diff line number Diff line
@@ -947,7 +947,8 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, 
	return clk;

}



static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,

static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,

				struct samsung_pll_clock *pll_clk,

				void __iomem *base)

{

	struct samsung_clk_pll *pll;
@@ -1066,7 +1067,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, 
		return;

	}



	samsung_clk_add_lookup(clk, pll_clk->id);

	samsung_clk_add_lookup(ctx, clk, pll_clk->id);



	if (!pll_clk->alias)

		return;
@@ -1077,11 +1078,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, 
			__func__, pll_clk->name, ret);

}



void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,

void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,

			struct samsung_pll_clock *pll_list,

			unsigned int nr_pll, void __iomem *base)

{

	int cnt;



	for (cnt = 0; cnt < nr_pll; cnt++)

		_samsung_clk_register_pll(&pll_list[cnt], base);

		_samsung_clk_register_pll(ctx, &pll_list[cnt], base);

}