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Commit 911480cd authored by Xiaozhe Shi's avatar Xiaozhe Shi
Browse files

power: qpnp-smbcharger: allow configuration of aicl rerun period 



Add the dtsi property qcom,aicl-rerun-period-s in order to allow for the
configuration of how often AICL is reran in hardware.

CRs-Fixed: 920791
Change-Id: Id262f26b409d75f7c82ee79b25c4258baed43840
Signed-off-by: default avatarXiaozhe Shi <xiaozhes@codeaurora.org>
parent 86e47fbe

Documentation/devicetree/bindings/power/qpnp-smbcharger.txt

+3 −0
Original line number Diff line number Diff line
@@ -237,6 +237,9 @@ Optional Properties: 
				this property will not adjust the AICL deglitch time

				dynamically for handling the battery over-voltage

				oscillations when the charger is headroom limited.

- qcom,aicl-rerun-period-s	If force-aicl-rerun is on, this property dictates

				how often aicl is reran in seconds. Possible values

				are 45, 90, 180, and 360.

- qcom,ibat-ocp-threshold-ua	Maximum current before the battery will trigger

				overcurrent protection. Use the recommended

				battery pack value minus some margin.

drivers/power/qpnp-smbcharger.c

+50 −10
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ struct smbchg_version_tables { 
	int				iterm_ma_len;

	const int			*fcc_comp_table;

	int				fcc_comp_len;

	const int			*aicl_rerun_period_table;

	int				aicl_rerun_period_len;

	int				rchg_thr_mv;

};
@@ -124,6 +126,7 @@ struct smbchg_chip { 
	int				bmd_pin_src;

	int				jeita_temp_hard_limit;

	int				sw_esr_pulse_current_ma;

	int				aicl_rerun_period_s;

	bool				use_vfloat_adjustments;

	bool				iterm_disabled;

	bool				bmd_algo_disabled;
@@ -1235,6 +1238,13 @@ static const int fcc_comp_table_8996[] = { 
	1500,

};



static const int aicl_rerun_period[] = {

	45,

	90,

	180,

	360,

};



static void use_pmi8994_tables(struct smbchg_chip *chip)

{

	chip->tables.usb_ilim_ma_table = usb_ilim_ma_table_8994;
@@ -1246,6 +1256,8 @@ static void use_pmi8994_tables(struct smbchg_chip *chip) 
	chip->tables.fcc_comp_table = fcc_comp_table_8994;

	chip->tables.fcc_comp_len = ARRAY_SIZE(fcc_comp_table_8994);

	chip->tables.rchg_thr_mv = 200;

	chip->tables.aicl_rerun_period_table = aicl_rerun_period;

	chip->tables.aicl_rerun_period_len = ARRAY_SIZE(aicl_rerun_period);

}



static void use_pmi8996_tables(struct smbchg_chip *chip)
@@ -1259,6 +1271,8 @@ static void use_pmi8996_tables(struct smbchg_chip *chip) 
	chip->tables.fcc_comp_table = fcc_comp_table_8996;

	chip->tables.fcc_comp_len = ARRAY_SIZE(fcc_comp_table_8996);

	chip->tables.rchg_thr_mv = 150;

	chip->tables.aicl_rerun_period_table = aicl_rerun_period;

	chip->tables.aicl_rerun_period_len = ARRAY_SIZE(aicl_rerun_period);

}



#define CMD_CHG_REG	0x42
@@ -1327,6 +1341,32 @@ static int smbchg_set_dc_current_max(struct smbchg_chip *chip, int current_ma) 
				DCIN_INPUT_MASK, dc_cur_val);

}



#define AICL_WL_SEL_CFG			0xF5

#define AICL_WL_SEL_MASK		SMB_MASK(1, 0)

static int smbchg_set_aicl_rerun_period_s(struct smbchg_chip *chip,

								int period_s)

{

	int i;

	u8 reg;



	i = find_smaller_in_array(chip->tables.aicl_rerun_period_table,

			period_s, chip->tables.aicl_rerun_period_len);



	if (i < 0) {

		dev_err(chip->dev, "Cannot find %ds in aicl rerun period\n",

				period_s);

		return -EINVAL;

	}



	reg = i & AICL_WL_SEL_MASK;



	pr_smb(PR_STATUS, "aicl rerun period set to %ds\n",

			chip->tables.aicl_rerun_period_table[i]);

	return smbchg_sec_masked_write(chip,

			chip->dc_chgpth_base + AICL_WL_SEL_CFG,

			AICL_WL_SEL_CFG, reg);

}



static struct power_supply *get_parallel_psy(struct smbchg_chip *chip)

{

	if (!chip->parallel.avail)
@@ -6119,9 +6159,6 @@ static inline int get_bpd(const char *name) 
#define FG_INPUT_FET_DELAY_BIT		BIT(3)

#define TRIM_OPTIONS_7_0		0xF6

#define INPUT_MISSING_POLLER_EN_BIT	BIT(3)

#define AICL_WL_SEL_CFG			0xF5

#define AICL_WL_SEL_MASK		SMB_MASK(1, 0)

#define AICL_WL_SEL_45S		0

#define CHGR_CCMP_CFG			0xFA

#define JEITA_TEMP_HARD_LIMIT_BIT	BIT(5)

#define HVDCP_ADAPTER_SEL_MASK		SMB_MASK(5, 4)
@@ -6192,14 +6229,15 @@ static int smbchg_hw_init(struct smbchg_chip *chip) 
			chip->revision[DIG_MAJOR], chip->revision[DIG_MINOR],

			chip->revision[ANA_MAJOR], chip->revision[ANA_MINOR]);



	rc = smbchg_sec_masked_write(chip,

			chip->dc_chgpth_base + AICL_WL_SEL_CFG,

			AICL_WL_SEL_MASK, AICL_WL_SEL_45S);

	if (chip->aicl_rerun_period_s > 0) {

		rc = smbchg_set_aicl_rerun_period_s(chip,

				chip->aicl_rerun_period_s);

		if (rc < 0) {

			dev_err(chip->dev, "Couldn't set AICL rerun timer rc=%d\n",

					rc);

			return rc;

		}

	}



	rc = smbchg_sec_masked_write(chip, chip->usb_chgpth_base + TR_RID_REG,

			FG_INPUT_FET_DELAY_BIT, FG_INPUT_FET_DELAY_BIT);
@@ -6733,6 +6771,8 @@ static int smb_parse_dt(struct smbchg_chip *chip) 
			chip->parallel.min_9v_current_thr_ma);

	OF_PROP_READ(chip, chip->jeita_temp_hard_limit,

			"jeita-temp-hard-limit", rc, 1);

	OF_PROP_READ(chip, chip->aicl_rerun_period_s,

			"aicl-rerun-period-s", rc, 1);



	/* read boolean configuration properties */

	chip->use_vfloat_adjustments = of_property_read_bool(node,