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Commit 90a88643 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: set FORCE_ARB_IDLE_PLANES workaround 



Commit 1544d9d5 added a workaround
inside haswell_init_clock_gating and mentioned it is "a workaround for
early silicon revisions and should be removed later". This workaround
is documented in bit 31 of PRI_CTL. I asked Arthur and he mentioned
that setting FORCE_ARB_IDLE_PLANES replaces that workaround for the
newer machines. So use the new one.

Also notice that there's still another workaround for PRI_CTL that
involves WM_DBG, but it's not the one we're reverting. And notice that
we were previously setting WM_DBG_DISALLOW_MULTIPIPE_LP which disables
the LP watermarks when more than one pipe is used, and we really don't
want this because we need the LP watermarks if we want to reach deeper
PC states.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add a comment for the w/a name Ville dug out of Bspec.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3e1f7266

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3711,6 +3711,9 @@ 
# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	(1 << 5)

# define CHICKEN3_DGMG_DONE_FIX_DISABLE		(1 << 2)



#define CHICKEN_PAR1_1		0x42080

#define  FORCE_ARB_IDLE_PLANES	(1 << 14)



#define DISP_ARB_CTL	0x45000

#define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)

#define  DISP_FBC_WM_DIS		(1<<15)

drivers/gpu/drm/i915/intel_pm.c

+3 −8
Original line number Diff line number Diff line
@@ -4172,14 +4172,9 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
	/* WaSwitchSolVfFArbitrationPriority:hsw */

	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);



	/* XXX: This is a workaround for early silicon revisions and should be

	 * removed later.

	 */

	I915_WRITE(WM_DBG,

			I915_READ(WM_DBG) |

			WM_DBG_DISALLOW_MULTIPLE_LP |

			WM_DBG_DISALLOW_SPRITE |

			WM_DBG_DISALLOW_MAXFIFO);

	/* WaRsPkgCStateDisplayPMReq:hsw */

	I915_WRITE(CHICKEN_PAR1_1,

		   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);



	lpt_init_clock_gating(dev);

}