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Commit 3e1f7266 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
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drm/i915: MCH_SSKPD is a 64 bit register on Haswell 



And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
the new one is not zero.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 85a02deb

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -4633,7 +4633,7 @@ void intel_init_pm(struct drm_device *dev) 
			}

			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;

		} else if (IS_HASWELL(dev)) {

			if (SNB_READ_WM0_LATENCY()) {

			if (I915_READ64(MCH_SSKPD)) {

				dev_priv->display.update_wm = haswell_update_wm;

				dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;

			} else {