Loading arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +12 −4 Original line number Diff line number Diff line Loading @@ -213,8 +213,10 @@ iommus = <&mdp_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mdp_axi_clk"; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { Loading @@ -222,8 +224,10 @@ iommus = <&rot_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "rot_axi_clk"; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { Loading @@ -231,8 +235,10 @@ iommus = <&mdp_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mdp_axi_clk"; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { Loading @@ -240,8 +246,10 @@ iommus = <&rot_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "rot_axi_clk"; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; mdss_fb0: qcom,mdss_fb_primary { Loading Loading
arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +12 −4 Original line number Diff line number Diff line Loading @@ -213,8 +213,10 @@ iommus = <&mdp_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mdp_axi_clk"; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { Loading @@ -222,8 +224,10 @@ iommus = <&rot_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "rot_axi_clk"; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { Loading @@ -231,8 +235,10 @@ iommus = <&mdp_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mdp_axi_clk"; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { Loading @@ -240,8 +246,10 @@ iommus = <&rot_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "rot_axi_clk"; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; mdss_fb0: qcom,mdss_fb_primary { Loading