Loading arch/arm/boot/dts/qcom/msm8937-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -646,6 +646,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU0>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -661,6 +663,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU1>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -676,6 +680,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU2>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -691,6 +697,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU3>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -706,6 +714,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU4>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -721,6 +731,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU5>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -736,6 +748,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU6>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -751,6 +765,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU7>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading Loading
arch/arm/boot/dts/qcom/msm8937-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -646,6 +646,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU0>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -661,6 +663,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU1>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -676,6 +680,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU2>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -691,6 +697,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU3>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -706,6 +714,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU4>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -721,6 +731,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU5>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -736,6 +748,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU6>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading @@ -751,6 +765,8 @@ coresight-nr-inports = <0>; coresight-cti-cpu = <&CPU7>; qcom,cti-save; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; Loading