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Commit 8b85143e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux into next/soc2 

From Jason Cooper:
mvebu soc changes for v3.10

 - use the mvebu-mbus driver
 - prep for LPAE support

Depends:
 - mvebu/cleanup (tags/cleanup_for_v3.10)
 - mvebu/drivers (tags/drivers_for_v3.10)

* tag 'soc_for_v3.10' of git://git.infradead.org/users/jcooper/linux

:
  ARM: mvebu: Align the internal registers virtual base to support LPAE
  ARM: mvebu: Limit the DMA zone when LPAE is selected
  arm: plat-orion: remove addr-map code
  arm: mach-mv78xx0: convert to use the mvebu-mbus driver
  arm: mach-orion5x: convert to use mvebu-mbus driver
  arm: mach-dove: convert to use mvebu-mbus driver
  arm: mach-kirkwood: convert to use mvebu-mbus driver
  arm: mach-mvebu: convert to use mvebu-mbus driver
  bus: mvebu: fix mistake in PCIe window target attribute for Kirkwood
  bus: mvebu-mbus: Restore checking for coherency fabric hardware
  ARM: Orion: add dbg_show function to gpio-orion driver
  bus: introduce an Marvell EBU MBus driver
  arm: mach-orion5x: use mv_mbus_dram_info() in PCI code
  arm: plat-orion: use mv_mbus_dram_info() in PCIe code
  arm: plat-orion: only build addr-map.c when needed

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 567b1b08 da497f6f

arch/arm/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -562,6 +562,7 @@ config ARCH_DOVE 
	select PINCTRL_DOVE

	select PLAT_ORION_LEGACY

	select USB_ARCH_HAS_EHCI

	select MVEBU_MBUS

	help

	  Support for the Marvell Dove SoC 88AP510
@@ -575,6 +576,7 @@ config ARCH_KIRKWOOD 
	select PINCTRL

	select PINCTRL_KIRKWOOD

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell Kirkwood series SoCs:

	  88F6180, 88F6192 and 88F6281.
@@ -586,6 +588,7 @@ config ARCH_MV78XX0 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell MV78xx0 series SoCs:

	  MV781x0, MV782x0.
@@ -598,6 +601,7 @@ config ARCH_ORION5X 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell Orion 5x series SoCs:

	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),

arch/arm/boot/dts/armada-370-xp.dtsi

+0 −5
Original line number Diff line number Diff line
@@ -73,11 +73,6 @@ 
			       clocks = <&coreclk 2>;

		};



		addr-decoding@d0020000 {

			compatible = "marvell,armada-addr-decoding-controller";

			reg = <0xd0020000 0x258>;

		};



		sata@d00a0000 {

			compatible = "marvell,orion-sata";

			reg = <0xd00a0000 0x2400>;

arch/arm/include/debug/mvebu.S

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
*/



#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000

#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000

#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000



	.macro	addruart, rp, rv, tmp

	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE

arch/arm/mach-dove/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y				+= common.o addr-map.o irq.o

obj-y				+= common.o irq.o

obj-$(CONFIG_DOVE_LEGACY)	+= mpp.o

obj-$(CONFIG_PCI)		+= pcie.o

obj-$(CONFIG_MACH_DOVE_DB)	+= dove-db-setup.o

arch/arm/mach-dove/addr-map.c

deleted100644 → 0
+0 −125
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-dove/addr-map.c

 *

 * Address map functions for Marvell Dove 88AP510 SoC

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/mbus.h>

#include <linux/io.h>

#include <asm/mach/arch.h>

#include <asm/setup.h>

#include <mach/dove.h>

#include <plat/addr-map.h>

#include "common.h"



/*

 * Generic Address Decode Windows bit settings

 */

#define TARGET_DDR		0x0

#define TARGET_BOOTROM		0x1

#define TARGET_CESA		0x3

#define TARGET_PCIE0		0x4

#define TARGET_PCIE1		0x8

#define TARGET_SCRATCHPAD	0xd



#define ATTR_CESA		0x01

#define ATTR_BOOTROM		0xfd

#define ATTR_DEV_SPI0_ROM	0xfe

#define ATTR_DEV_SPI1_ROM	0xfb

#define ATTR_PCIE_IO		0xe0

#define ATTR_PCIE_MEM		0xe8

#define ATTR_SCRATCHPAD		0x0



static inline void __iomem *ddr_map_sc(int i)

{

	return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));

}



/*

 * Description of the windows needed by the platform code

 */

static struct __initdata orion_addr_map_cfg addr_map_cfg = {

	.num_wins = 8,

	.remappable_wins = 4,

	.bridge_virt_base = BRIDGE_VIRT_BASE,

};



static const struct __initdata orion_addr_map_info addr_map_info[] = {

	/*

	 * Windows for PCIe IO+MEM space.

	 */

	{ 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,

	  TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE

	},

	{ 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,

	  TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE

	},

	{ 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,

	  TARGET_PCIE0, ATTR_PCIE_MEM, -1

	},

	{ 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,

	  TARGET_PCIE1, ATTR_PCIE_MEM, -1

	},

	/*

	 * Window for CESA engine.

	 */

	{ 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,

	  TARGET_CESA, ATTR_CESA, -1

	},

	/*

	 * Window to the BootROM for Standby and Sleep Resume

	 */

	{ 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,

	  TARGET_BOOTROM, ATTR_BOOTROM, -1

	},

	/*

	 * Window to the PMU Scratch Pad space

	 */

	{ 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,

	  TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1

	},

	/* End marker */

	{ -1, 0, 0, 0, 0, 0 }

};



void __init dove_setup_cpu_mbus(void)

{

	int i;

	int cs;



	/*

	 * Disable, clear and configure windows.

	 */

	orion_config_wins(&addr_map_cfg, addr_map_info);



	/*

	 * Setup MBUS dram target info.

	 */

	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;



	for (i = 0, cs = 0; i < 2; i++) {

		u32 map = readl(ddr_map_sc(i));



		/*

		 * Chip select enabled?

		 */

		if (map & 1) {

			struct mbus_dram_window *w;



			w = &orion_mbus_dram_info.cs[cs++];

			w->cs_index = i;

			w->mbus_attr = 0; /* CS address decoding done inside */

					  /* the DDR controller, no need to  */

					  /* provide attributes */

			w->base = map & 0xff800000;

			w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);

		}

	}

	orion_mbus_dram_info.num_cs = cs;

}