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Commit da497f6f authored by Lior Amsalem's avatar Lior Amsalem Committed by Jason Cooper
Browse files

ARM: mvebu: Align the internal registers virtual base to support LPAE 



In order to be able to support the LPAE, the internal registers
virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
earlyprintk we map the internal registers and it must be section
aligned.

Signed-off-by: default avatarLior Amsalem <alior@marvell.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 99ff0561

arch/arm/include/debug/mvebu.S

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
*/



#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000

#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000

#define ARMADA_370_XP_REGS_VIRT_BASE	0xfec00000



	.macro	addruart, rp, rv, tmp

	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE

arch/arm/mach-mvebu/armada-370-xp.h

+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
#define __MACH_ARMADA_370_XP_H



#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000

#define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfeb00000)

#define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfec00000)

#define ARMADA_370_XP_REGS_SIZE		SZ_1M



/* These defines can go away once mvebu-mbus has a DT binding */